Ferroelectric Double Gate Memory Cell for Low Voltage Retention
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Solution Overview
Problem
Conventional nonvolatile ferroelectric memory devices face challenges in scaling down, leading to degraded retention characteristics and difficulty in performing random access operations due to low voltage stress, especially in nano-scale levels, and are prone to data destruction in NAND type cell arrays.
Innovation Solution
The implementation of a nonvolatile ferroelectric memory device with a NOR type cell array using a nano-scale Double Gate Cell structure, featuring a ferroelectric layer and a floating channel layer, where the polarity state of the ferroelectric layer affects the resistance of the floating channel layer, and a switch unit controlled by a selection line to manage read and write operations, allowing for low-voltage operation and high-speed performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of the memory cell is scaled down to nano scale, then the storage density is improved, but the retention characteristic degrades
Solution Approach 1:
The channel region is divided into two gates (first gate and second gate) positioned at opposite sides, creating a double-gate structure. This segmentation allows independent control of each gate to compensate for voltage stress and maintain retention characteristics in scaled-down nano-scale cells
Solution Approach 2:
Different gates are applied with different voltages based on local requirements. The first gate and second gate can be biased independently to create optimal electric field distribution in different regions of the channel, improving retention without increasing overall cell size
2Device complexity
If a NAND type cell array is used, then the device complexity is reduced, but the random access operation becomes difficult due to data destruction in unselected cells
Solution Approach 1:
The cell array is organized as a NOR type array where memory cells are connected in parallel between bit lines and word lines, enabling independent access to any cell without affecting others. This segmentation of access paths prevents data destruction in unselected cells during random access operations
Solution Approach 2:
Instead of using NAND type connection where cells are connected in series requiring sequential access, the patent inverts the approach by using NOR type connection with parallel paths, allowing any cell to be accessed independently without disturbing others, thus enabling true random access
3Device complexity
If a conventional single gate structure is used, then the device complexity is reduced, but the retention characteristic degrades under low voltage stress
Solution Approach 1:
The channel is controlled by two separate gates instead of one, allowing the voltage stress to be distributed and managed independently. This segmentation enables better retention characteristics under low voltage conditions by optimizing the electric field in each gate region
Solution Approach 2:
The patent changes the electrical parameters by applying different voltages to the first gate and second gate independently. This parameter control allows optimization of the electric field distribution to maintain retention characteristics while operating at lower voltages
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances retention characteristics and enables high-speed operations by effectively controlling read and write operations with low voltage, preventing data destruction and improving random access capabilities compared to conventional devices.
Implementation Method 1
a first double gate cell for storing a bit of datum, the first double gate cell including a ferroelectric layer and a floating channel layer, wherein a polarity state of the ferroelectric layer affects a resistance of the floating channel layer
Data Source
AI summary
A nonvolatile ferroelectric memory device has a plurality of ferroelectric memory cells. The ferroelectric memory cells include a first double gate cell for storing a bit of datum, the first double gate cell including a ferroelectric layer and a floating channel layer, wherein a polarity state of the ferroelectric layer affects a resistance of the floating channel layer, the resistance of the floating channel layer corresponding to the bit of datum stored in the first double gate cell; and a second double gate cell selectively turned on by a potential on a selection line to supply a potential of a sense line to the first double gate cell to control read and write operations of the first double gate cell. The present invention also provides methods for operating the nonvolatile ferroelectric memory device.