Nanoinformatics TRIZ Cases

A carbon nanotube thin film transistor method grows single-walled tubes via chemical vapor deposition and transfers them to an insulating substrate.

Parallel shot processing reduces filling time and boosts throughput in photo-nanoimprint systems.

Light filters with microscopic structures produce unique optical patterns that resolve authentication security weaknesses in telecommunication networks.

Vertical stacking of active regions and lower interconnection layers enhances integration density while reducing interconnection complexity.

A short period superlattice layer uses lateral transparent and conductive regions to balance light transmission and current flow.

Plasma oxidation creates a protective oxide layer on nanosheet structures, preventing etch-back during sacrificial material removal to improve insulation.

An interlayer between the Mo/Si reflective film and Ru layer prevents oxidation, maintaining EUV reflectance stability.

A magnetic tunnel junction splits its free layer into read-sensing and storage segments to enable multi-state data retention.

Chaperonin protein lattices trap nanocrystals to ensure uniform size and spatial distribution, addressing fabrication complexity limits.

A mold peeling method determines contact region geometry to locate its center of gravity and applies force at that point for efficient separation.

A semiconductor device integrates a blocking insulation film to protect epitaxial regions during gate formation.

Distributed sync marks resynchronize the write clock during data writing, reducing jitter and cross-talk on patterned hard disk media.

A segmented master hierarchy replicates micro-optical structures into plastically deformable material for wafer-scale production.

Non-conductive filler material separates the bottom gate from source and drain regions in GAA transistors, reducing parasitic capacitance and leakage current.

Multijunction organic photovoltaics combine solution and vacuum processed layers to resolve the tradeoff between optical absorption and electrical resistance.

A superlattice nanodevice structure uses a catalyst-free growth mechanism to form one-dimensional nanostructures on a substrate.

A nano-sheet transistor device uses sacrificial layer etching to form a replacement gate structure around a reduced-thickness channel.

Nitrogen-substituted graphene laminated with metal particles reduces electrical resistance and prevents corrosion in transparent electrodes.

Fluorinated curable compositions improve high-aspect ratio patternability and repeatability in nanoimprint lithography.

A micro/nanometer structured imprinting device transfers patterns directly onto the active surface of an injection molding tool.

A method forming a bottom insulating layer in cavities created by etching sacrificial layers underneath channel regions.

Dynamic gate voltages replace fixed barriers to resolve control complexity and enable single-electron detection.

A hexagonal cell array assigns fluid drops to unassigned cells based on predetermined volumes and recursive neighbor distribution.

Automated image classification replaces manual inspection, reducing fabrication time while maintaining high accuracy for quantum material evaluation.

Differential nanoribbon spacing accommodates thick gate dielectrics, reducing leakage currents in high-voltage transistors.

Transfer silicon nanowires to insulation substrates using alignment marks, eliminating complex e-beam lithography and reducing production costs.

Electron-donating polymers with specific repeating units absorb light across a wide wavelength region.

A ferroelectric double gate memory cell uses a floating channel layer to store data bits via polarity state changes.

High permeability side shields intercept stray flux to maintain cross-track resolution while reducing shield-to-shield spacing for higher recording density.

A block copolymer guide layer directs microphase separation to form self-assembled patterns with high dimensional accuracy.

Epitaxial source-drain regions with distinct impurity compositions mitigate short channel effects in fin structures, improving gate control.

A metal-insulator-metal waveguide guides plasmonic signals through a dielectric layer, enabling miniaturization beyond optical diffraction limits.

A nanowire PIN tunnel field effect transistor uses oblique ion implantation to create precise n-type and p-type doped regions.

A top emission organic light emitting device uses a charge-transfer complex and fullerene layer to prevent metal oxide formation that reduces lifetime.

Absorbent layer reflects ultraviolet inspection light to enhance mask contrast for narrow patterns.

A high-ratio insulating layer reduces leakage currents and limits capacitive coupling in all-around gate transistors by blocking substrate paths.

Segmented micro-elements measure temperature and impedance while a pressure sensor prevents excessive force that damages tissue.

Thermal chemical vapor deposition controls zinc oxide crystallographic plane orientation using source materials that reduce polar plane surface energy.

A semiconductor device with a core-shell nanowire structure grown on polycrystalline silicon.

Side layers apply compression stress to stabilize the magnetization pinned layer, preventing direction fluctuations under high temperature environments.

Nano-Si in porous SiO2 replaces degradable materials to ensure CMOS compatibility and reliable data retention.

Segmented EUV mask absorber resolves pattern accuracy versus reflected light contradiction by optimizing local thickness for phase shift and absorption.

A titanium-rich titanium nitride bottom electrode supports carbon nanotube metal-insulator-metal memory stacks.

Halogen-containing gases suppress germanium segregation at silicon germanium interfaces, enabling thinner transition layers and faster silicon growth rates.

High-pressure selective oxidation on SiGe sidewalls reduces parasitic capacitance, enhancing device performance.

Dummy gate segmentation and sacrificial layer removal resolve isotropic etching trade-offs, improving gate morphology and device reliability.