Magnetic Memory Device Vertical Stacking Integration
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Solution Overview
Problem
The demand for semiconductor memory devices with faster operating speeds and lower power consumption is increasing, and existing magnetic memory devices face challenges in achieving higher integration density and reduced power consumption.
Innovation Solution
A spin-orbit-torque-based magnetic memory device is designed with a substrate having a top and bottom surface, featuring a first and second active region with channel and source/drain patterns, a gate electrode, and a lower interconnection layer containing a magnetic tunnel junction pattern and a spin-orbit torque line. This configuration allows for vertical stacking of transistors and placement of the magnetic tunnel junction pattern and spin-orbit torque line in the lower interconnection layer, reducing interconnection complexity and enabling higher integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If magnetic memory devices use traditional planar integration, then manufacturing is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from planar integration to three-dimensional vertical stacking by placing the magnetic tunnel junction pattern and spin-orbit torque line in a lower interconnection layer beneath the transistor active regions. This vertical arrangement enables higher integration density while managing interconnection complexity through stratified layer organization.
2Speed
If magnetic memory devices increase operating speed, then data access improves, but power consumption increases
Solution Approach 1:
The patent extracts the magnetic tunnel junction pattern and spin-orbit torque line from the traditional transistor gate region and places them in a separate lower interconnection layer. This spatial separation allows independent optimization of the magnetic storage component, enabling high-speed operation with reduced power consumption by eliminating the need for high-current pulse delivery through the transistor gate.
3Loss of energy
If magnetic memory devices reduce power consumption, then energy efficiency improves, but integration density decreases
Solution Approach 1:
The patent embeds the magnetic tunnel junction pattern and spin-orbit torque line within the lower interconnection layer, nesting the magnetic storage functionality within the interconnection structure itself. This nested arrangement enables multiple functions (storage, switching, and interconnection) to coexist in a compact vertical footprint, achieving both low power consumption and high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design enhances integration density and reduces the complexity of the interconnection structure, allowing for efficient data storage and retrieval while minimizing power consumption, thus addressing the demands for faster and more efficient semiconductor memory devices.
Implementation Method 1
The MTJ pattern includes two magnetic layers and an insulating layer interposed therebetween. Resistance of the MTJ pattern may vary depending on magnetization directions of the magnetic layers relative to one another. For example, the electrical resistance of the MTJ pattern is higher when magnetization directions of the magnetic layers are anti-parallel to each other compared to when they are parallel to each other.
Implementation Method 2
a spin-orbit torque line in the lower interconnection layer
Data Source
AI summary
A magnetic memory device includes a substrate having top and bottom surfaces, a first active region on the top surface of the substrate, the first active region including a lower channel pattern and a lower source/drain pattern, a second active region stacked on the first active region, the second active region including an upper channel pattern and an upper source/drain pattern, a gate electrode on the lower and upper channel patterns and extending in a first direction, a lower interconnection layer on the bottom surface of the substrate, a magnetic tunnel junction pattern and a spin-orbit torque line in the lower interconnection layer, a first lower contact electrically connecting the lower source/drain pattern to the magnetic tunnel junction pattern, and a second lower contact electrically connecting the upper source/drain pattern to the spin-orbit torque line.