Transistor Bottom Insulating Layer Formation
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Solution Overview
Problem
Existing methods for forming horizontal channel transistor structures face complexity in applying electrical insulation to mitigate charge carrier leakage, especially at more aggressive device dimensions.
Innovation Solution
A method involving the formation of semiconductor layer stacks with sacrificial layers and channel layers, where the sacrificial layers are selectively removed to create cavities filled with insulating material, forming a bottom insulating layer underneath the transistor structures, which extends uninterrupted beneath the source, drain, and channel regions, supported by an insulating wall.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing processing techniques are used to form bottom insulation, then electrical insulation is provided, but the process becomes relatively complex and challenging to apply at aggressive device dimensions
Solution Approach 1:
The bottom insulating layer is formed before the channel layers are created, establishing the insulation foundation in advance. This preliminary action simplifies subsequent processing steps and enables better control at aggressive device dimensions, as the insulation structure is already in place to guide further fabrication
Solution Approach 2:
The bottom insulating layer is formed in a separate preliminary step before channel layer formation, dividing the complex insulation process into distinct manageable stages. This segmentation allows each step to be optimized independently, reducing overall process complexity while maintaining insulation effectiveness
2Shape
If bottom insulating layer is formed after channel layers, then channel structures are established, but the insulating layer cannot extend uninterrupted underneath source, drain and channel regions
Solution Approach 1:
The bottom insulating layer is formed in advance before channel layers are created, allowing it to extend continuously underneath all future source, drain, and channel regions. This preliminary formation ensures uninterrupted insulation coverage without requiring complex subsequent steps to bridge gaps or repair discontinuities
Solution Approach 2:
The bottom insulating layer serves multiple functions simultaneously: it provides electrical insulation for future source, drain, and channel regions, acts as a structural foundation for channel layer formation, and enables self-aligned gate patterning. This multi-functionality is achieved because the layer is formed in advance to cover all required areas continuously
3Reliability
If conventional insulation methods are used, then charge carrier leakage is mitigated, but mask edge placement errors increase at advanced technology nodes
Solution Approach 1:
The bottom insulating layer structure enables self-aligned gate stack patterning, where the gate alignment is determined by the pre-formed insulating layer and channel structures rather than relying solely on mask alignment. This self-alignment mechanism automatically compensates for mask edge placement variations, maintaining manufacturing precision at advanced technology nodes while preserving leakage mitigation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the formation of transistor structures by providing effective electrical insulation, reducing the risk of leakage and allowing for self-aligned gate stack patterning, while being compatible with advanced technology nodes and reducing mask edge placement errors.
Implementation Method 1
by etching removing the sacrificial layer of each layer stack to form a respective cavity on either sides of the insulating wall underneath the channel layer
Implementation Method 2
depositing a bottom insulating material in said cavities
Data Source
AI summary
According to an aspect of the present inventive concept there is provided a method for forming a first and a second transistor structure, wherein the first and second transistor structures are spaced apart by an insulating wall, and the method comprising:forming on a semiconductor layer of the substrate a first semiconductor layer stack and a second semiconductor layer stack, each layer stack comprising in a bottom-up direction a sacrificial layer and a channel layer, wherein the layer stacks are spaced apart by a trench extending into the semiconductor layer substrate, the trench being filled with an insulating wall material to form the insulating wall; andprocessing the layer stacks to form the first and second transistor structures in the first and second device regions, respectively, the processing comprising forming source and drain regions and forming gate stacks;the method further comprising, prior to said processing:by etching removing the sacrificial layer of each layer stack to form a respective cavity on either sides of the insulating wall underneath the channel layer of the first and second layer stack, the channel layers being supported by the insulating wall; anddepositing a bottom insulating material in said cavities;wherein, subsequent to said processing, the bottom insulating material forms a bottom insulating layer underneath the source region, the drain region and the channel regions on either side of the insulating wall.