Nanowire Oxidation for Parasitic Capacitance Control
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in forming channel structures for horizontal gate-all-around (hGAA) device structures with controlled parasitic capacitance, as conventional methods often result in increased manufacturing difficulty and degraded device performance due to large parasitic capacitance between the metal gate and source/drain regions.
Innovation Solution
A method involving a selective oxidation process is employed, where a multi-material layer with alternating silicon and SiGe layers is used, with the oxidation layer predominantly formed on the SiGe layer sidewalls under high process pressure (>5 bar), effectively reducing parasitic capacitance by controlling the oxidation selectivity greater than 5:1.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to form channel structures for hGAA devices, then manufacturing process is simpler, but parasitic capacitance between metal gate and source/drain regions increases, degrading device performance
Solution Approach 1:
The patent applies local quality by creating a selective oxidation layer only on specific sidewalls of the nanowire structures. The oxidation layer is formed on the second group of sidewalls in the second layer of the multi-material layer, while leaving other sidewalls unaffected. This localized modification reduces parasitic capacitance at critical interfaces between the metal gate and source/drain regions, thereby improving device performance without requiring complete structural redesign
Solution Approach 2:
The patent utilizes parameter changes by controlling the oxidation process under high pressure conditions (greater than 5 bar). This pressure parameter modification enables selective oxidation with a selectivity ratio greater than 5:1 between different sidewall groups, allowing precise control over where the oxidation layer forms. The pressure parameter change transforms the oxidation behavior to achieve the desired parasitic capacitance reduction
2Reliability
If different materials are used to form nanowire channel structures, then device performance can be optimized, but manufacturing difficulty increases due to integration challenges
Solution Approach 1:
The patent applies segmentation by dividing the nanowire channel structure into a multi-material layer with repeating pairs of different material layers. Each layer can be independently formed and controlled, allowing optimization of device performance through material selection while maintaining manufacturing feasibility through modular layer-by-layer fabrication processes
Solution Approach 2:
The patent applies local quality by implementing selective oxidation on specific sidewalls of the multi-material structure. This localized treatment addresses integration challenges by modifying only the critical interfaces where parasitic capacitance occurs, while leaving other portions of the complex multi-material structure unchanged, thereby reducing manufacturing difficulty
3Reliability
If oxidation layer is formed on all sidewalls, then uniform protection is achieved, but parasitic capacitance is not reduced and device performance is degraded
Solution Approach 1:
The patent applies local quality by forming the oxidation layer exclusively on the second group of sidewalls in the second layer, while leaving the first group of sidewalls and other layers unaffected. This selective localization reduces parasitic capacitance at the metal gate-source/drain interfaces without compromising the structural integrity of the entire nanowire system
Solution Approach 2:
The patent applies inversion by reversing the conventional approach of uniform oxidation. Instead of oxidizing all sidewalls uniformly, the process selectively oxidizes only specific sidewalls (the second group in the second layer), inverting the traditional mindset and achieving superior device performance by targeted modification
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance and minimizes device leakage, enhancing the electrical performance of hGAA structures by maintaining controlled interfaces between nanowires and source/drain regions.
Implementation Method 1
selectively forming an oxidation layer on the second group of sidewalls in the second layer
Implementation Method 2
maintaining a process pressure at greater than 5 bar
Data Source
AI summary
The present disclosure provide methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes supplying an oxygen containing gas mixture to a multi-material layer on a substrate in a processing chamber, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, the first and the second layers having a first group and a second group of sidewalls respectively exposed through openings defined in the multi-material layer, maintaining a process pressure at greater than 5 bar, and selectively forming an oxidation layer on the second group of sidewalls in the second layer.