Nano-Sheet Transistor Gate Stack Design for Leakage Control
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Solution Overview
Problem
The challenge in forming nano-sheet transistor devices is the limited physical space for the gate structure, which restricts the ability to achieve desired operational characteristics such as threshold voltages and low leakage currents, especially as device dimensions shrink and the number of layers in the gate stack increases.
Innovation Solution
A method involving the formation of a patterned stack of materials with sacrificial layers above a semiconductor substrate, followed by etching processes to reduce the thickness of these layers, allowing for a thicker gate stack and a replacement gate structure that accommodates a reduced-thickness channel semiconductor material layer, enabling a more flexible and efficient gate structure design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate insulation layer is made thicker to reduce leakage currents, then the device exhibits lower leakage currents, but the physical space for the gate structure becomes insufficient as device dimensions shrink
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional gate-all-around structure that wraps around the channel region. This dimensional change allows the gate to control the channel from multiple directions (top, bottom, and sides), effectively increasing the gate's control volume without proportionally increasing the planar footprint, thereby accommodating thicker gate stacks in limited space
Solution Approach 2:
The gate structure is positioned within a recess formed in the substrate, creating a nested configuration where the gate stack is embedded into the substrate volume. This nesting approach utilizes the vertical dimension of the substrate to house the thicker gate stack, preserving lateral space while accommodating increased gate thickness for leakage control
2Adaptability or versatility
If more layers of material are added to the gate stack to achieve desired operational characteristics, then the device exhibits improved operational characteristics, but the physical space for the gate structure becomes even more constrained
Solution Approach 1:
By implementing a gate-all-around structure, the patent utilizes three-dimensional space to accommodate multiple gate stack layers. The gate wraps around the channel, providing control from top, bottom, and lateral directions, which allows stacking of multiple functional layers (insulation, conductive, work-function adjusting) without proportionally increasing the planar area
Solution Approach 2:
The gate structure employs a composite multi-layer stack comprising different materials (high-k insulation materials, conductive metals, work-function adjusting layers) with distinct functional properties. This composite approach enables tailored operational characteristics (threshold voltage, leakage control, conductivity) within a compact vertical architecture, maximizing functional versatility in limited space
3Speed
If the channel region is made thinner to improve device speed, then the device operates faster, but the gate structure has less space to accommodate all necessary materials
Solution Approach 1:
The gate-all-around structure extends the gate control into the vertical dimension by wrapping around the thin channel region. This three-dimensional configuration increases the effective gate-channel interface area without increasing the lateral dimensions, allowing the channel to remain thin for high-speed operation while the gate maintains adequate space for multiple material layers through vertical and lateral wrapping
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of nano-sheet transistor devices with improved operational characteristics, such as reduced leakage currents and enhanced flexibility in designing advanced IC products, by increasing the physical space for the gate structure and enabling better control over the gate stack composition and thickness.
Implementation Method 1
performing at least one first etching process through the replacement gate cavity to selectively remove at least a portion of the first and second layers of sacrificial material
Implementation Method 2
performing at least one second etching process through the replacement gate cavity to reduce the initial thickness of a portion of the at least one channel semiconductor material layer
Data Source
AI summary
A method that includes forming a patterned stack of materials comprising at least one channel semiconductor material layer and first and second layers of sacrificial material positioned above and below, respectively, the at least one channel semiconductor material layer, forming a replacement gate cavity above the patterned stack of materials and performing an etching process through the gate cavity to selectively remove at least a portion of the first and second layers of sacrificial material relative to the at least one channel semiconductor material layer. The method further includes performing a second etching process to form a reduced-thickness portion of the channel semiconductor material layer that has a final thickness that is less than the initial thickness and forming a replacement gate structure around at least the reduced-thickness portion of the channel semiconductor material layer.