Nanowire Transistor Gate Interface via Dummy Gate Segmentation
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Solution Overview
Problem
Conventional methods for forming nanowire devices face challenges in achieving a good interface between the nanowire and the gate, leading to difficulties in maintaining flat gate morphology and degrading device performance due to isotropic etching processes.
Innovation Solution
A method involving the formation of a semiconductor substrate with fin structures, patterned dummy gates, and spacers to create recessed regions, followed by epitaxial growth of source and drain regions, and the use of high K dielectric and metal gates to improve the interface quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If isotropic etching process is used to remove material under nanowire, then material removal is achieved, but gate morphology becomes poor and interface quality degrades
Solution Approach 1:
The patent segments the material removal process into multiple stages: first removing material laterally to form trenches, then removing material vertically from the trenches. This segmentation allows each etching step to be optimized independently, achieving both good gate morphology and complete material removal without requiring complex single-step isotropic etching
Solution Approach 2:
The patent performs preliminary actions by forming sacrificial layers and dummy gates before the final nanowire structure is complete. These preliminary structures guide the selective etching process, ensuring that material is removed in a controlled sequence that preserves interface quality while enabling complete underlying material removal
2Reliability
If conventional gate patterning is used, then gate structure is formed, but interface between nanowire and gate deteriorates
Solution Approach 1:
The patent introduces dummy gates and sacrificial layers as intermediary structures that facilitate the formation of the final gate-nanowire interface. These intermediaries are temporarily formed, used to guide selective material removal, and then removed themselves, leaving a clean interface between the nanowire and the final gate structure without direct contact between the problematic etching process and the interface region
Solution Approach 2:
Instead of directly patterning the gate over the nanowire channel, the patent inverts the approach by first forming dummy gates and using them to define regions for selective material removal. The actual gate is then formed after the interface is prepared, ensuring that the gate-nanowire interface is created under controlled conditions rather than during the patterning step
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables the formation of nanowire devices with improved gate characteristics and better control over the gate, allowing for more effective on/off switching.
Implementation Method 1
this requires an isotropic etching process
Implementation Method 2
performing epitaxial growth on both sides of the semiconductor layer to form source and drain regions
Data Source
AI summary
A method for forming a semiconductor device includes forming a semiconductor substrate having at least one fin structure on an insulator on a substrate. The fin structure includes a semiconductor layer overlying a sacrificial layer. The method also includes forming a patterned dummy gate on the substrate, forming a first spacer on both sides of the dummy gate, and using the dummy gate and the first spacer as a mask to remove a portion of the semiconductor layer and the sacrificial layer. Then the sacrificial layer is etched to form recessed regions on both sides of the sacrificial layer, and a second spacer is formed to cover both sides of the sacrificial layer and expose both sides of the semiconductor layer. The method also includes performing epitaxial growth on both sides of the semiconductor layer to form source and drain regions.