GAA Transistors with Shallow Source/Drain Regions
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Solution Overview
Problem
The reduction in size of gate-all-around (GAA) transistors leads to increased parasitic capacitance, which limits their performance and contributes to unwanted power consumption and leakage current.
Innovation Solution
The introduction of a non-conductive filler material adjacent to the bottom gate section in GAA transistors, allowing the source and drain regions to be grown on top of the filler, reducing the overlap and thus minimizing parasitic capacitance between the gate and source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the size of GAA transistors is reduced to conserve die area, then more computing power can be made available in devices of the same size, but parasitic capacitance increases which limits performance and increases power consumption
Solution Approach 1:
A filler material is introduced as an intermediary between the bottom gate section and the source/drain regions. This filler material displaces conductive material that would otherwise be in direct contact with the bottom gate, thereby reducing parasitic capacitance. The filler acts as a mediator that eliminates the harmful capacitive coupling while allowing the compact GAA transistor structure to be maintained.
2Area of moving object
If the size of GAA transistors is reduced, then die area is conserved, but parasitic capacitance increases contributing to unwanted leakage current
Solution Approach 1:
The filler material serves as an intermediary that eliminates direct conductive paths between the bottom gate section and source/drain regions. By replacing conductive material with non-conductive or low-conductivity filler material in the overlapping region, parasitic capacitance is reduced, thereby minimizing leakage current while preserving the compact transistor design.
3Device complexity
If source and drain regions are positioned adjacent to the bottom gate section, then device structure is compact, but parasitic capacitance between gate and source/drain regions increases
Solution Approach 1:
The filler material is positioned in the region where source/drain regions would otherwise directly overlap with the bottom gate section. This intermediary material eliminates the direct capacitive coupling between conductive elements while maintaining the compact three-dimensional structure of the GAA transistor, thereby reducing parasitic capacitance without increasing device complexity.
Data Source
AI summary
Gate-all-around (GAA) transistors with shallow source/drain regions and methods of fabricating the same provide a GAA transistor that includes one or more channels positioned between a source region and a drain region. The one or more channels, which may be nanowire, nanosheet, or nanoslab semiconductors, are surrounded along a longitudinal axis by gate material. At a first end of the channel is a source region and at an opposite end of the channel is a drain region. To reduce parasitic capacitance between a bottom gate and the source and drain regions, a filler material is provided adjacent the bottom gate, and the source and drain regions are grown on top of the filler material. In this fashion, the bottom gate does not abut the source region or the drain region, reducing geometries which would contribute to parasitic capacitance.