Ferroelectric Dielectric Stack for High Capacitance Low Leakage
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Solution Overview
Problem
As semiconductor chip feature sizes decrease, there is a challenge in maintaining sufficient capacitance in capacitor and transistor devices while minimizing leakage current and ensuring high breakdown voltage, which existing high-k materials struggle to address effectively.
Innovation Solution
A semiconductor device is designed with a ferroelectric layer implementing negative capacitance and a dielectric structure with a superlattice configuration, where the ferroelectric and dielectric layers are electrically connected in series, enhancing capacitance while maintaining low leakage current and high breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If high-k materials are used to increase capacitance, then capacitance is improved, but leakage current increases and breakdown voltage decreases
Solution Approach 1:
The patent employs a composite dielectric structure combining a ferroelectric layer (e.g., hafnium zirconium oxide) with a non-ferroelectric high-k dielectric layer. This composite architecture leverages the negative capacitance property of the ferroelectric layer to enhance overall capacitance while the non-ferroelectric layer provides stable electrical characteristics, low leakage current, and high breakdown voltage, thus resolving the contradiction between high capacitance and reliability
Solution Approach 2:
The patent modifies the physical and chemical parameters of the dielectric materials by controlling the composition ratio (e.g., Hf and Zr ratios in hafnium zirconium oxide), thickness, and crystalline structure of the ferroelectric and non-ferroelectric layers. These parameter adjustments enable optimization of capacitance while maintaining low leakage current and high breakdown voltage characteristics
2Area of moving object
If feature size decreases, then device density is improved, but capacitance maintenance becomes difficult
Solution Approach 1:
The composite dielectric structure with negative capacitance effect enables achieving high capacitance in reduced device areas. The ferroelectric layer's negative capacitance amplifies the overall capacitance without requiring proportional increases in physical dimensions, allowing capacitance maintenance despite feature size reduction
Solution Approach 2:
By adjusting the thickness and composition parameters of the ferroelectric and non-ferroelectric layers, the patent optimizes capacitance density per unit area. This enables maintaining sufficient total capacitance even as the overall device footprint decreases
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases capacitance beyond that of the dielectric layer alone, while maintaining low leakage current and high breakdown voltage, thereby addressing the capacitance requirements of shrinking semiconductor devices.
Implementation Method 1
a ferroelectric layer disposed on the first electrode that implements a negative capacitance
Data Source
AI summary
A semiconductor device includes a first electrode, a ferroelectric layer disposed on the first electrode and implementing a negative capacitance, a dielectric structure disposed on the ferroelectric layer and including a first dielectric layer and a second dielectric layer that are alternately stacked, and a second electrode disposed on the dielectric structure. The ferroelectric layer and the dielectric structure are configured to be electrically connected in series to each other. The ferroelectric layer and dielectric structure together have a non-ferroelectric property.