Ferroelectric Gate Dielectric Segmentation for 3D Memory Reliability
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Solution Overview
Problem
Current semiconductor devices face challenges in ensuring structural stability and operational reliability, particularly as design rules decrease and integration increases, necessitating improved storage cell structures that can maintain reliability in three-dimensional configurations.
Innovation Solution
A semiconductor device incorporating a ferroelectric material with a gate dielectric layer comprising both ferroelectric and non-ferroelectric portions, where the ferroelectric portion is in contact with the gate electrode and the non-ferroelectric portion is in contact with the interlayer insulation layer, enhancing memory cell reliability by suppressing polarization interference among neighboring cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a three-dimensional storage cell structure is adopted to increase integration density, then device complexity and integration increase, but structural stability and operational reliability deteriorate due to polarization interference among neighboring cells
Solution Approach 1:
The gate dielectric layer is segmented into distinct ferroelectric and non-ferroelectric portions, creating spatial separation between functional regions. This segmentation isolates the polarization effects to specific areas (ferroelectric portions contacting gate electrodes) while non-ferroelectric portions act as barriers, preventing polarization interference from propagating to adjacent cells and thereby maintaining reliability in high-density 3D structures
Solution Approach 2:
Different portions of the gate dielectric layer are assigned different material properties: ferroelectric portions are placed where polarization storage is needed (contacting gate electrodes), while non-ferroelectric portions are placed where polarization blocking is needed (contacting interlayer insulation layers). This local differentiation of material quality enables simultaneous achievement of high integration density through 3D stacking and operational reliability through localized suppression of harmful polarization effects
2Manufacturing precision
If design rules are decreased to improve manufacturing precision, then manufacturing precision improves, but structural stability deteriorates in three-dimensional configurations
Solution Approach 1:
The gate dielectric layer employs a composite structure combining ferroelectric and non-ferroelectric materials in specific spatial arrangements. This composite approach allows the use of thinner layers (benefiting from decreased design rules) while maintaining structural stability through the complementary properties of the constituent materials - the non-ferroelectric portions providing structural integrity and polarization blocking, and the ferroelectric portions providing the desired electrical functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of ferroelectric and non-ferroelectric portions in the gate dielectric layer improves the operational reliability of memory cells in three-dimensional structures by effectively managing polarization, thereby enhancing storage operations and memory cell density.
Implementation Method 1
Crystallization heat treatment is performed to the amorphous ferroelectric material layer in contact with the crystallization seed layer
Implementation Method 2
A crystallization seed layer in contact with the amorphous ferroelectric material layer and the interlayer insulation layer is formed. Crystallization heat treatment is performed to the amorphous ferroelectric material layer in contact with the crystallization seed layer
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a substrate, an electrode stack disposed on the substrate, the electrode stack including an interlayer insulation layer and a gate electrode structure that are alternately stacked in a direction perpendicular to the substrate, a trench penetrating the electrode stack to expose sidewall surfaces of the interlayer insulation layer and the gate electrode structure, a gate dielectric layer disposed along a sidewall surface of the trench, the gate dielectric layer including a ferroelectric portion and a non-ferroelectric portion, and a channel layer disposed to adjacent to the gate dielectric layer. The ferroelectric portion is in contact with the gate electrode structure, and the non-ferroelectric portion is in contact with the interlayer insulation layer.