Ferroelectric Gate Stack Using AlScN and AlScOC at Scaled Thickness
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Solution Overview
Problem
Conventional ferroelectric materials used in semiconductor devices face challenges in achieving stable and reliable ferroelectric responses at scaled thicknesses, limiting their performance in transistor applications.
Innovation Solution
The integration of a p-type aluminum scandium oxycarbide (AlScOC) layer with a ferroelectric aluminum scandium nitride (AlScN) layer in a field effect transistor structure, combined with other p-type semiconducting oxide and ferroelectric layer pairs, to form thin-film or 3D transistors with enhanced ferroelectric properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ferroelectric materials are used in gate structures, then ferroelectric response can be achieved, but stability and reliability deteriorate at scaled thicknesses
Solution Approach 1:
The patent employs composite material structures including p-type aluminum scandium oxycarbide (AlScOC) semiconductor layers combined with ferroelectric aluminum scandium nitride (AlScN) layers. These composite structures enable stable ferroelectric responses at scaled thicknesses by combining materials with complementary properties, where the p-type oxide semiconductor provides both semiconducting and ferroelectric characteristics.
Solution Approach 2:
The patent utilizes parameter changes by adjusting the composition and doping levels of the ferroelectric materials. Specifically, scandium doping in aluminum nitride layers and controlling the stoichiometry of oxycarbide layers allows optimization of ferroelectric properties while maintaining stability at reduced thicknesses suitable for advanced technology nodes.
2Productivity
If ferroelectric material thickness is reduced for scaling, then device density improves, but ferroelectric response stability deteriorates
Solution Approach 1:
Composite structures of p-type oxide semiconductors with ferroelectric nitride layers provide enhanced stability at scaled thicknesses. The interfacial engineering between these materials creates favorable band alignment and reduces defects, maintaining ferroelectric response even when total gate dielectric thickness is reduced for higher device density.
Solution Approach 2:
The patent applies local quality by creating specific interface regions with optimized properties. The p-type oxide semiconductor layers are engineered to provide favorable interface characteristics with the ferroelectric layers, ensuring stable ferroelectric response locally at the critical interface regions while enabling overall thickness reduction.
3Stability of the object's composition
If p-type oxide semiconductor layers are used, then electrostatic stability improves, but manufacturing complexity increases
Solution Approach 1:
The patent merges the functions of the semiconductor channel layer and the gate dielectric layer into a single p-type oxide semiconductor layer that exhibits both semiconducting and ferroelectric properties. This consolidation reduces the number of interfaces and simplifies the manufacturing process while maintaining electrostatic stability.
Solution Approach 2:
The p-type oxide semiconductor layers serve multiple functions simultaneously: they act as the semiconductor channel, provide the gate dielectric function with ferroelectric properties, and ensure favorable interface characteristics. This multi-functionality reduces overall device complexity while maintaining performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the development of stable and reliable ferroelectric field effect transistors with improved performance, suitable for full complementary circuit applications entirely based on oxides, enhancing electrostatic stability and conductivity.
Implementation Method 1
A ferroelectric material includes a spontaneous electric polarization that can be reversed by changing an electrical field applied to the ferroelectric material
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a gate layer, a semiconductor layer and a ferroelectric layer disposed between the gate layer and the semiconductor layer. The semiconductor layer includes a first material containing a Group III element, a rare-earth element and a Group VI element, the ferroelectric layer includes a second material containing a Group III element, a rare-earth element and a Group V element and the gate layer includes a third material containing a Group III element and a rare-earth element. A method of fabricating a semiconductor device is also provided.