Ferroelectric Gate Stacks Reduce Subthreshold Swing in 2D Material FETs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional field effect transistors (FETs) face limitations in switching speed due to high subthreshold swing (SS) and limited control over gate operation, which restricts their performance in semiconductor devices.
Innovation Solution
The use of multiple channel regions formed in two-dimensional (2D) material layers, combined with multiple gate stacks that include layers of ferroelectric material with negative capacitance, enhances gate control and reduces subthreshold swing, thereby improving switching speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional FET structures are used, then device simplicity is maintained, but switching speed is limited due to high subthreshold swing
Solution Approach 1:
The gate stack is segmented into multiple independent gate electrodes (first gate electrode, second gate electrode, third gate electrode) that can be independently controlled. This segmentation allows separate optimization of different gate functions, enabling enhanced switching speed through coordinated gate operation while maintaining manageable device complexity through modular architecture
Solution Approach 2:
The patent employs a nested gate structure where multiple gate electrodes are positioned at different vertical levels and spatial locations. The first gate electrode is positioned over the channel region, the second gate electrode is positioned over the first gate electrode, and the third gate electrode is positioned over the second gate electrode. This nesting arrangement maximizes gate control volume without proportionally increasing footprint, thereby improving switching speed while controlling device complexity
2Speed
If gate control is enhanced to reduce subthreshold swing, then switching speed improves, but device footprint increases
Solution Approach 1:
The patent transitions from planar gate configuration to three-dimensional stacked gate architecture. Multiple gate electrodes are arranged in vertical layers rather than spreading horizontally, utilizing the vertical dimension to enhance gate control. This dimensional change allows achieving reduced subthreshold swing and improved switching speed without increasing device footprint, as the enhanced control is accomplished through vertical stacking rather than horizontal expansion
3Ease of operation
If multiple gate stacks are used to improve control, then gate control is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary patterning actions where mandrel structures are formed first, followed by spacer deposition and mandrel removal to define gate electrode regions. This preliminary action approach simplifies the fabrication of complex multi-gate structures by breaking down the manufacturing process into manageable sequential steps, thereby enhancing gate control while mitigating manufacturing complexity
Solution Approach 2:
The patent uses spacer structures as intermediary elements that facilitate the formation of complex gate electrode patterns. The spacers are deposited conformally on mandrels and then anisotropically etched to define the gate regions. This intermediary approach simplifies the direct patterning of multiple gate electrodes, enhancing gate control capability while reducing fabrication complexity by using spacers as self-aligned pattern definition tools
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for FET devices with higher switching speed and larger on-current without increasing footprint, offering improved performance compared to conventional FETs.
Implementation Method 1
The use of multiple channel regions formed in two-dimensional (2D) material layers, combined with multiple gate stacks that include layers of ferroelectric material with negative capacitance, enhances gate control and reduces subthreshold swing
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. A first gate stack is formed over a substrate, wherein the first gate stack comprises a first ferroelectric layer. A source/channel/drain stack is formed over the first gate stack, wherein the source/channel/drain stack comprises one or more 2D material layers. A second gate stack is formed over the source/channel/drain stack, wherein the second gate stack comprises a second ferroelectric layer.