Ferroelectric Layer Fabrication Using Low-Directional I-PVD
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Solution Overview
Problem
As semiconductor devices shrink in size, the non-ferro phase in ferroelectric materials occupies a larger area in ferroelectric random access memory (FeRAM) cells, leading to variations in ferroelectric characteristics and reduced yield rates due to small memory windows.
Innovation Solution
A method for fabricating FeRAM cells involves depositing a top electrode layer using a low-directional Ionized Physical Vapor Deposition (I-PVD) process to control the ratio of ferro and non-ferro phases in the ferroelectric layer, ensuring a higher percentage of ferro phase post-recrystallization, thereby improving ferroelectric behavior and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down in size, then production efficiency increases and costs decrease, but the non-ferro phase occupies a larger area in FeRAM cells leading to variations in ferroelectric characteristics and reduced yield rates
Solution Approach 1:
The patent applies parameter changes by modifying the deposition process parameters (using low-directional I-PVD instead of conventional PVD) to control the crystal phase composition in the ferroelectric layer. This process parameter change ensures a higher percentage of ferro phase (>40%) in scaled-down FeRAM cells, thereby maintaining ferroelectric characteristics and yield rates despite device size reduction
Solution Approach 2:
The patent utilizes phase transitions by controlling the crystallization process to promote the formation of the ferroelectric phase (orthorhombic or tetragonal) over the non-ferroelectric phase (monoclinic). The low-directional I-PVD deposition method induces favorable stress conditions that drive phase transition toward the desired ferroelectric phase, ensuring proper ferroelectric behavior in miniaturized devices
2Ease of manufacture
If the ratio of non-ferro phase increases in scaled-down FeRAM cells, then manufacturing becomes simpler, but ferroelectric behavior deteriorates and memory window decreases
Solution Approach 1:
The patent changes the deposition parameter from conventional PVD to low-directional I-PVD, which fundamentally alters the film formation mechanism. This parameter change enables better control over crystal phase distribution and composition, achieving uniform ferroelectric characteristics across the device array while maintaining manufacturing feasibility
3Productivity
If conventional PVD process is used to deposit top electrode layer, then deposition is faster and simpler, but the ferro phase ratio in ferroelectric layer cannot be controlled to be above 40%, resulting in poor ferroelectric behavior
Solution Approach 1:
The patent transitions from conventional PVD to low-directional I-PVD, changing the physical state and directional characteristics of the deposition process. This parameter change enables simultaneous achievement of adequate deposition efficiency and precise control over ferro phase ratio (>40%), resolving the contradiction between speed and precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the ferroelectric behavior and uniformity of FeRAM cells, increasing the ferro phase area to above 40% and improving the memory window, thus enhancing the yield and performance of small-sized FeRAM cells.
Implementation Method 1
performing a first ionized physical deposition process to deposit a top electrode layer over the ferroelectric layer
Implementation Method 2
ensuring a higher percentage of ferro phase post-recrystallization
Data Source
AI summary
A method for fabricating a semiconductor device is provided. The method includes depositing a ferroelectric layer over the substrate; performing a first ionized physical deposition process to deposit a top electrode layer over the ferroelectric layer; patterning the top electrode layer into a top electrode; and patterning the ferroelectric layer to into a ferroelectric element below the top electrode.


