Ferroelectric Layer Sidewall Protrusion for Memory Reliability
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Solution Overview
Problem
Current semiconductor devices face challenges in maintaining structural stability and reliable signal storage operations, particularly in ferroelectric memory devices, where the integration of ferroelectric layers with gate structures is complex and prone to errors due to undesired remanent polarization caused by voltage interactions.
Innovation Solution
The semiconductor device incorporates a ferroelectric layer disposed along the sidewall surface of a gate structure with alternately stacked gate electrode and interlayer insulation layers, featuring protruding portions to increase the ferroelectric layer's area, which enhances the number of crystal grains and remanent polarization states, thereby improving memory storage performance by controlling polarization orientation through external electric fields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the ferroelectric layer area is increased to improve memory storage performance, then the number of signal information states and memory window performance increase, but the device complexity and manufacturing difficulty increase due to the need for precise protruding structure formation
Solution Approach 1:
The gate electrode layer is divided into multiple segments with different protrusion heights, creating distinct first and second gate electrode layers. This segmentation allows the ferroelectric layer to have different areas over different regions, increasing the number of crystal grains and remanent polarization states without requiring a completely different structure, thus improving memory storage performance while managing complexity through modular design
Solution Approach 2:
The invention introduces a vertical dimension variation by making the gate electrode layer protrude at different heights in different regions. This dimensional change creates the protruding structure that increases the ferroelectric layer area and crystal grain count, enabling enhanced memory performance without increasing planar footprint, thereby balancing performance improvement with acceptable device complexity
2Reliability
If alternately stacked gate electrode and interlayer insulation layers are used to control polarization orientation, then remanent polarization states increase, but the manufacturing precision requirements increase due to alternating stacking complexity
Solution Approach 1:
The interlayer insulation layer is formed to protrude in advance before the gate electrode layer is deposited. This preliminary action creates a pre-defined template that guides the subsequent gate electrode formation, ensuring proper alignment and reducing the precision requirements for the alternating stacking process, as each layer can be formed sequentially with reference to the previous protruding structure
Solution Approach 2:
The interlayer insulation layer acts as an intermediary structure between substrate layers, providing a physical template and spacing reference that facilitates the formation of alternately stacked gate electrode and interlayer insulation layers. This intermediary structure simplifies the manufacturing process by reducing direct alignment requirements between gate electrode layers, thereby improving manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the number of signal information states and memory window performance by stabilizing ferroelectric properties and reducing errors in write and read operations, leading to enhanced memory storage capabilities.
Implementation Method 1
Studies on ferroelectric memory devices, for use for example in semiconductor devices, that are capable of non-volatile storage of electrical signals and realization of the electrical signals at multiple levels are being conducted
Implementation Method 2
controlling polarization orientation through external electric fields
Data Source
AI summary
A semiconductor device according to an embodiment includes a substrate, and a gate structure disposed over the substrate. The gate structure includes a hole pattern including a central axis extending in a direction perpendicular to a surface of the substrate. The gate structure includes a gate electrode layer and an interlayer insulation layer, which are alternately stacked along the central axis. The semiconductor device includes a ferroelectric layer disposed adjacent to a sidewall surface of the gate electrode layer inside the hole pattern, and a channel layer disposed adjacent to the ferroelectric layer inside the hole pattern. In this case, one of the gate electrode layer and the interlayer insulation layer protrudes toward the central axis of the hole pattern relative to the other one of the gate electrode layer and the interlayer insulation layer.