Ferroelectric Majority-Gate Ripple Carry Adder With Fewer Transistors
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Solution Overview
Problem
Existing 1-bit full adders in CMOS logic require numerous transistors, leading to high power consumption and area usage, which is a challenge for devices aiming for lower power consumption.
Innovation Solution
Implementing 1-bit full adders using non-linear polar material-based majority, minority, and threshold gates that eliminate switching transistors and reduce interconnect routings, utilizing ferroelectric or paraelectric capacitors for charge storage and low voltage operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional CMOS logic gates (AND, OR, XOR) are used to build 1-bit full adders, then the adder can perform addition function, but the number of transistors increases leading to high power consumption and large area
Solution Approach 1:
The patent replaces traditional CMOS transistor-based logic gates with a different computational mechanism using floating body transistors where charge storage in the body region replaces conventional gate control mechanisms. This substitution fundamentally changes the computing paradigm from voltage-controlled to charge-state-controlled logic, achieving lower power consumption and reduced transistor count
Solution Approach 2:
The invention changes the operating parameters by utilizing the body effect and charge storage characteristics of transistors. By controlling the charge state in the transistor body rather than using traditional gate voltages, the circuit achieves logic functionality with fewer transistors and lower power consumption while maintaining the addition function
2Area of stationary object
If traditional CMOS logic gates are used in 1-bit full adders, then the adder circuit can be implemented, but the area occupied by the circuit increases due to multiple transistors
Solution Approach 1:
The patent merges multiple transistor functions into fewer transistors by utilizing the floating body charge storage capability. A single floating body transistor can perform logic operations that traditionally required multiple transistors, thereby reducing the overall circuit area while maintaining full adder functionality
Solution Approach 2:
By replacing the conventional transistor switching mechanism with a charge-state based mechanism in floating body transistors, the patent achieves more compact circuit implementation. The charge storage in the body region enables logic functionality with reduced transistor count and smaller area occupation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in compact adder circuitry with significantly reduced power consumption and area, allowing processors to operate at lower voltages and enter low power states without data loss, while maintaining performance.
Implementation Method 1
ferroelectric or paraelectric capacitors for charge storage
Implementation Method 2
ferroelectric or paraelectric capacitors for charge storage
Data Source
AI summary
A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and/or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.