3D Ferroelectric Memory Back-Gate Interconnect Layout for Reliability
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity and maintaining electrical reliability, particularly due to limitations in the integration and control of back gate electrodes in three-dimensional memory cell arrays.
Innovation Solution
The semiconductor device incorporates a structure with vertically stacked gate electrodes, ferroelectric material layers, and channel layers, along with upper and lower interconnection structures, which include back gate interconnections disposed above and below the vertical structures to improve electrical characteristics and reduce ferroelectric disturbance defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but electrical characteristics and reliability deteriorate due to integration challenges
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional vertical stacking, where gate electrodes are stacked vertically above each other with vertical structures passing through them. This dimensional change enables increased storage capacity while maintaining electrical control through the introduction of back gate electrodes that can be independently controlled from the rear side of the substrate.
Solution Approach 2:
The memory device is divided into functionally independent front and back sides. The front side contains the conventional gate electrodes and control circuitry, while the back side contains the back gate electrodes and their interconnection structures. This segmentation allows independent optimization and control of front and back gates, improving electrical characteristics and reliability by enabling separate voltage control for better threshold adjustment and disturbance reduction.
2Reliability
If back gate electrodes are integrated in three-dimensional structures, then electrical characteristics are improved, but device complexity increases due to additional interconnection structures
Solution Approach 1:
The back gate interconnection structures are extracted and placed on the back side of the substrate, separate from the front side gate control circuitry. This extraction simplifies the overall device complexity by isolating the back gate control paths from the front gate control paths, allowing each side to be optimized independently without interfering with the other's interconnection complexity.
Solution Approach 2:
The back gate interconnection structures are nested within the vertical structures, with contact plugs positioned at specific heights along the vertical channels. The lower back gate interconnections are nested below the vertical structures while upper back gate interconnections are nested above them, creating a compact three-dimensional integration that reduces overall device complexity despite the additional functional elements.
3Quantity of substance
If vertical structures with ferroelectric material layers are used, then data storage capacity is increased, but ferroelectric disturbance defects increase
Solution Approach 1:
The back gate electrodes provide a feedback control mechanism for the ferroelectric material layers. By applying compensating voltages through the back gates, the system can counteract unwanted polarization states and reduce disturbance defects in the ferroelectric material, thereby maintaining data integrity while preserving the high storage capacity enabled by the vertical ferroelectric structure.
Solution Approach 2:
The back gate electrodes are configured to apply preliminary counteracting electric fields that prevent ferroelectric disturbance defects before they occur. By controlling the back gate voltages, the system can preemptively stabilize the ferroelectric polarization states and prevent disturbance propagation, reducing defects while maintaining the high-capacity three-dimensional storage structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the electrical characteristics and reliability of the semiconductor device by efficiently using space for interconnections, improving integration, and minimizing ferroelectric disturbance defects, thereby increasing data storage capacity.
Implementation Method 1
each of the vertical structures includes a back gate electrode, a ferroelectric material layer on a side surface of the back gate electrode
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
A semiconductor device (100) includes gate electrodes (130) extending in a first direction (X), first (VS1_1) and second (VS1_2) vertical structures passing through the gate electrodes, a first upper interconnection, and a second upper interconnection structure, the first and second vertical structures including a back gate electrode (150), a ferroelectric material layer (143), a channel layer (142), and a gate insulating layer (141), the first upper interconnection structure including bit lines (BL1, BL2) extending in a second direction (Y), a first contact plug (173a) connected to a lower surface of a first back gate electrode of the first vertical structure, and a first back gate interconnection (BG1) extending between the bit lines in the second direction and connected to the first contact plug, and the second upper interconnection structure including a second contact plug (173d) connected to an upper surface of a second back gate electrode of the second vertical structure, and a second back gate interconnection (BG4) extending in the second direction and connected to the second contact plug.