Ferroelectric Memory Cell Access via Pulsed Voltage Control
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Solution Overview
Problem
Ferroelectric memory cells face challenges in reducing stress and leakage during access operations, leading to increased power consumption and reduced memory cell lifespan due to the application of non-zero voltages for extended durations, which also disturbs neighboring cells.
Innovation Solution
A method is introduced where a memory cell is accessed by initially selecting the digit and word lines with a low plate voltage, then coupling unselected digit lines to the plate to minimize leakage, and subsequently coupling the selected digit line to the plate to reduce stress and prevent overshoot, allowing for reduced voltage application time and efficient data writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-zero voltage is applied to memory cell for extended duration to ensure complete access operation, then read/write reliability is improved, but power consumption increases and memory cell stress increases
Solution Approach 1:
The patent applies periodic voltage pulses instead of continuous voltage application. The controller applies voltage to the digit line and plate in discrete time intervals (first duration, second duration, third duration) rather than continuously, enabling the memory cell to complete read/write operations while minimizing total energy consumption through pulsed action.
Solution Approach 2:
The patent dynamically adjusts voltage application timing based on operational needs. The controller selectively applies voltage to different lines (digit line, plate, word line) at different times during the access operation, optimizing the voltage application profile to achieve reliable operations with reduced power consumption.
2Reliability
If non-zero voltage is applied to memory cell for extended duration to ensure complete access operation, then read/write reliability is improved, but memory cell lifespan decreases
Solution Approach 1:
The patent uses periodic voltage pulsing to reduce cumulative stress on the memory cell. By applying voltage in discrete intervals rather than continuously, the cell experiences shorter exposure to electrical stress, thereby extending its operational lifespan while maintaining read/write reliability.
Solution Approach 2:
The controller performs preliminary voltage application to the digit line and plate before the word line to prepare the memory cell for the write operation. This preliminary action ensures the cell is in the correct state before the actual write occurs, reducing the total voltage application time and stress on the cell.
3Productivity
If voltage is applied to selected digit line and plate to write logic state, then data writing is achieved, but neighboring memory cells are disturbed
Solution Approach 1:
The patent segments the voltage application process into distinct phases: first applying voltage to the digit line and plate, then applying voltage to the word line. This segmentation allows the selected memory cell to be written without simultaneously applying voltage to neighboring cells, thereby minimizing disturbance to adjacent cells while maintaining writing efficiency.
Solution Approach 2:
The controller applies voltage to the digit line and plate before applying voltage to the word line. This preliminary action establishes the correct voltage conditions for the selected cell before the write operation begins, ensuring that voltage is not applied to neighboring cells during the critical write phase.
4Measurement precision
If voltage is applied to digit line and plate to sense logic state, then reading is achieved, but stress on memory cell increases
Solution Approach 1:
The patent applies voltage periodically during the sensing operation rather than continuously. The controller applies voltage to the digit line and plate for a first duration to enable sensing, then maintains this state during a second duration without additional stress, reducing cumulative stress on the cell while maintaining sensing accuracy.
Data Source
AI summary
Methods, systems, and devices for accessing a ferroelectric memory cell are described. In some examples, during a first portion of an access procedure, the voltages of a digit line and word line coupled with the memory cell may be increased while the voltage of a plate coupled with the memory cell is held constant, which may support sensing a logic state stored by the memory cell prior the access procedure, and which may result in a first logic state being written to the memory cell. A voltage of the plate may then be increased, and the digit line may then be coupled with the plate. Because the first logic state was previously written to the memory cell, a target logic state may not need to be subsequently written to the memory cell unless different than the first logic state.