Ferroelectric Memory Cell Gate Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing ferroelectric (FE) memory cells face endurance issues due to charging at the FE-semiconductor interface and require large capacitors, complex fabrication sequences, leading to increased costs and reduced memory density.
Innovation Solution
The integration of a FE capacitor with a transistor gate, where the FE material is separated from the semiconductor channel by a gate dielectric and a conductor material, eliminating the FE-semiconductor interface and allowing for simpler, low-cost fabrication processes, dense memory arrays, and reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If FE material is directly contacted with semiconductor channel, then memory cell can be formed with simpler structure, but charging at FE-semiconductor interface causes endurance issues
Solution Approach 1:
An intermediate layer (gate dielectric or conductor material) is introduced between the FE material and semiconductor channel to prevent direct contact. This intermediary layer eliminates the harmful charging effect at the interface while maintaining the overall simplicity of the memory cell structure, thus resolving the contradiction between structural simplicity and reliability.
2Quantity of substance
If large capacitor is used in memory cell, then sufficient storage capacity is achieved, but memory density is reduced
Solution Approach 1:
The capacitor and transistor gate are merged into a single integrated structure where the FE capacitor shares the gate electrode and gate dielectric layers with the transistor. This merging eliminates redundant components and reduces the overall area required for each memory cell, thereby increasing memory density while maintaining sufficient storage capacity.
Solution Approach 2:
The gate structure serves dual functions: it acts as both the control gate for the transistor and one electrode of the FE capacitor. This multi-functionality reduces the number of separate components needed, allowing smaller cell area while preserving the required capacitance for data storage.
3Manufacturing precision
If complex fabrication sequence is used, then precise manufacturing is achieved, but fabrication cost and process complexity increase
Solution Approach 1:
The fabrication processes for the capacitor and transistor are merged into a single sequence. The gate dielectric and gate electrode layers are formed once and serve both as transistor gate components and capacitor components. This eliminates the need for separate capacitor fabrication steps, reducing process complexity while maintaining manufacturing precision through standardized CMOS-compatible processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances memory cell endurance, reduces fabrication complexity and costs, and enables the formation of dense memory arrays with minimal parasitic capacitance, improving overall performance.
Implementation Method 1
a gate dielectric provided over at least a portion of the semiconductor material
Implementation Method 2
a FE capacitor integrated with a transistor gate... reduced parasitic capacitance
Data Source
AI summary
Described herein are ferroelectric (FE) memory cells that include transistors having gates with FE capacitors integrated therein. An example memory cell includes a transistor having a semiconductor channel material, a gate dielectric over the semiconductor material, a first conductor material over the gate dielectric, a FE material over the first conductor material, and a second conductor material over the FE material. The first and second conductor materials form, respectively, first and second capacitor electrodes of a capacitor, where the first and second capacitor electrodes are separated by the FE material (hence, a “FE capacitor”). Separating a FE material from a semiconductor channel material of a transistor with a layer of a gate dielectric and a layer of a first conductor material eliminates the FE-semiconductor interface that may cause endurance issues in some other FE memory cells.