Ferroelectric Memory Cell Using Contact Resistance Switching
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Solution Overview
Problem
Existing semiconductor devices face challenges in integration and functionality, particularly in ferroelectric-based non-volatile memory devices, where contact resistance switching and internal resistance switching characteristics affect device performance and integration.
Innovation Solution
A semiconductor device design that utilizes a ferroelectric pattern interposed between electrode patterns, where contact resistance is switched based on polarization direction changes in response to bias voltage, allowing for improved integration and functionality as a memory device, independent of internal resistance switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ferroelectric-based non-volatile memory devices utilize internal resistance switching, then memory functionality is achieved, but device performance and integration are limited due to short channel effects
Solution Approach 1:
The patent changes the switching mechanism parameter from internal resistance switching to contact resistance switching. By applying bias voltage to control the polarization direction of the ferroelectric pattern, the contact resistance between the electrode pattern and ferroelectric pattern is changed, enabling data storage without relying on internal resistance switching, thus improving integration while maintaining memory performance
Solution Approach 2:
The patent introduces a gate pattern as an intermediary element adjacent to the ferroelectric pattern. The gate pattern applies electric field to control the polarization direction of the ferroelectric pattern, which in turn modulates the contact resistance. This intermediary control mechanism enables precise switching without direct voltage application to the contact interface, reducing short channel effects and improving device integration
2Device complexity
If device dimensions are reduced for better integration, then integration is improved, but short channel effects increase and affect device performance
Solution Approach 1:
The patent replaces the traditional voltage-driven internal resistance switching mechanism with a field-controlled contact resistance switching mechanism. The gate pattern generates an electric field that controls the polarization direction of the ferroelectric pattern, which modulates the contact resistance. This field-controlled mechanism is less sensitive to short channel effects, allowing smaller device dimensions while maintaining performance
Solution Approach 2:
The gate pattern serves as an intermediary that decouples the voltage control from the contact interface. By controlling the ferroelectric pattern's polarization through the gate's electric field, the system avoids direct voltage stress at the contact interface, reducing short channel effects and enabling better scaling for improved integration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves improved integration and functionality by utilizing contact resistance switching, reducing the impact of short channel effects and enabling smaller device dimensions, while maintaining memory performance.
Implementation Method 1
a gate pattern adjacent to the ferroelectric pattern, and configured to control the direction of polarization of the ferroelectric pattern
Implementation Method 2
contact resistance between the ferroelectric pattern and the electrode pattern may be changed from a first resistance state to a second resistance state in response to a first bias voltage applied to the gate pattern
Data Source
AI summary
A method for operating a semiconductor device, the method according to the present invention includes applying a first bias voltage to a gate pattern, and storing first data in response to the first bias voltage, wherein contact resistance between an electrode pattern and a ferroelectric pattern is changed from a first resistance state to a second resistance state in response to the first bias voltage, the first data is stored based on the change from the first resistance state to the second resistance state, and the ferroelectric pattern is interposed between the gate pattern and the electrode pattern.