Ferroelectric Memory Stack With Doping Gradients for Multi-Bit States

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current memory devices lack the capability to implement multi-bit functionality effectively, which is essential for advanced data storage and processing applications, due to limitations in ferroelectric materials' ability to achieve multiple polarization states without significant changes in operating voltage.

Innovation Solution

A memory device is designed with a semiconductor substrate and multiple ferroelectric layers, including a first and second ferroelectric layer with doping concentration gradients, where the first layer has an increasing doping concentration and the second layer has a decreasing concentration, allowing for multi-bit functionality by adjusting the operating voltage based on hysteresis curves.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a single ferroelectric layer is used in the memory device, then the device structure remains simple, but the device cannot achieve multi-bit functionality with multiple polarization states

Engineering Contradiction:
Improvemulti-bit functionalityVSAvoidferroelectric layer structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The single ferroelectric layer is segmented into multiple distinct ferroelectric layers (first ferroelectric layer and second ferroelectric layer), each with different doping concentration gradients. This segmentation enables each layer to contribute differently to the overall polarization states, allowing the memory device to achieve multi-bit functionality by utilizing the combined polarization characteristics of the layered structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each ferroelectric layer is assigned a specific local quality through its unique doping concentration gradient profile. The first ferroelectric layer has a doping concentration that increases in a first direction, while the second ferroelectric layer has a doping concentration that increases in a second direction different from the first direction. This local quality differentiation enables each layer to exhibit distinct polarization characteristics, which when combined, provide multiple stable polarization states for multi-bit storage.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If ferroelectric layers with uniform doping concentration are used, then the manufacturing process is simpler, but the device cannot achieve multiple polarization states required for multi-bit operation

Engineering Contradiction:
Improvemultiple polarization statesVSAvoiddoping concentration control
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

Instead of using uniform doping concentration throughout the ferroelectric layers, the invention implements local quality variations by creating specific doping concentration gradients in each layer. The first ferroelectric layer has doping concentration increasing in a first direction, while the second ferroelectric layer has doping concentration increasing in a second direction. These localized doping variations enable each layer to contribute differently to the polarization states, achieving multiple stable polarization states necessary for multi-bit functionality.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The invention introduces directional dimensionality to the doping concentration distribution by specifying that the first ferroelectric layer has doping concentration increasing in a first direction while the second ferroelectric layer has doping concentration increasing in a second direction different from the first direction. This dimensional differentiation in doping profiles enables the creation of distinct polarization characteristics in each layer, which combine to provide multiple stable polarization states for multi-bit storage capability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution enables the memory device to achieve multi-bit functionality with multiple polarization states, enhancing data storage capacity and processing efficiency by effectively utilizing the ferroelectric layers' properties.

Implementation Method 1

Ferroelectrics refer to a material having ferroelectricity to maintain spontaneous polarization by aligning internal electric dipole moments

Methodology Applied
Scientific EffectFerroelectricity:

Implementation Method 2

The first ferroelectric layer has a doping concentration gradient in which a doping concentration increases in the first direction, and the second ferroelectric layer has a doping concentration gradient in which a doping concentration decreases in the first direction

Methodology Applied
Scientific EffectDoping concentration gradient: Dopants

Implementation Method 3

obtaining multiple-levels in different polarization states from each other by adjusting an operating voltage based on a hysteresis curve associated with the plurality of ferroelectric layers

Methodology Applied
Scientific EffectHysteresis: Hysteresis

Data Source

PatentUS20240260274A1Memory device implementing multi-bit and memory apparatus including the same
Publication Date: 2024.08.01 SAMSUNG ELECTRONICS CO LTD
  • US20240260274A1 patent drawing
  • US20240260274A1 patent drawing
  • US20240260274A1 patent drawing

AI summary

Provided are a memory device implementing multi-bit functionality and a memory apparatus including the memory device. The memory device includes a semiconductor substrate, a gate electrode on the semiconductor substrate, and a plurality of ferroelectric layers laminated between the semiconductor substrate and the gate electrode in a first direction perpendicular to a surface of the semiconductor substrate and including at least one first ferroelectric layer and at least one second ferroelectric layer. The first ferroelectric layer has a doping concentration gradient in which a doping concentration increases in the first direction, and the second ferroelectric layer has a doping concentration gradient in which a doping concentration decreases in the first direction. The memory device is configured to implement multi-bit functionality according to an operating voltage.