3D Ferroelectric Memory Cell Structure for Low-Power High-Density Storage
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in increasing data storage capacity while maintaining low power consumption and high operating speed.
Innovation Solution
A semiconductor memory device is designed with a three-dimensional structure incorporating a back gate electrode, a gate electrode, a channel layer, a ferroelectric layer, and a gate insulating layer, featuring a stacked structure with vertical structures and cell strings connected between a bit line and a common source line, utilizing ferroelectric materials for data storage with reduced program disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory cell arrangement is implemented to increase data storage capacity, then storage capacity is improved, but power consumption increases and operating speed decreases
Solution Approach 1:
The patent introduces a back gate electrode structure that enables independent voltage control of the channel layer, allowing optimization of threshold voltage and carrier concentration. This parameter control mechanism reduces leakage current in three-dimensional memory cells while maintaining storage capacity, thereby lowering power consumption without sacrificing the benefits of 3D stacking.
Solution Approach 2:
The patent employs a composite structure combining back gate electrode, gate insulating layer, and channel layer with specific material properties. This composite design enables efficient electric field control and charge storage in the three-dimensional configuration, achieving high capacity with reduced power consumption through optimized material interactions.
2Quantity of substance
If three-dimensional memory cell arrangement is implemented to increase data storage capacity, then storage capacity is improved, but operating speed decreases
Solution Approach 1:
The back gate electrode enables dynamic adjustment of channel conductivity and threshold voltage through independent voltage control. This parameter optimization accelerates charge injection and retrieval processes in three-dimensional memory cells, improving operating speed while maintaining the high storage capacity enabled by vertical stacking.
3Ease of manufacture
If conventional gate structure is used in three-dimensional memory, then manufacturing is simpler, but program disturbance occurs and performance is reduced
Solution Approach 1:
The patent divides the gate control function into two independent components: the conventional gate electrode and the back gate electrode. This segmentation allows independent optimization of program and erase operations, enabling precise control of charge injection while minimizing program disturbance to adjacent cells, thus improving reliability without significantly complicating the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves high data storage capacity with low power consumption and fast operating speed, minimizing program disturbance and improving reliability through the use of ferroelectric layers for data storage.
Implementation Method 1
a ferroelectric layer between the back gate electrode and the channel layer
Data Source
AI summary
A semiconductor memory device includes a back gate electrode, a gate electrode on the back gate electrode, a channel layer between the gate electrode and the back gate electrode, a gate insulating layer between the channel layer and the gate electrode, and a ferroelectric layer between the back gate electrode and the channel layer.