3D Ferroelectric Memory Pillar Structure for Lower Leakage
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Solution Overview
Problem
Existing ferroelectric memories face challenges in reducing device size and improving electrical performance, such as leakage current and parasitic capacitance, while maintaining compatibility with semiconductor manufacturing processes.
Innovation Solution
A ferroelectric memory structure is designed with a specific configuration including a substrate, conductive lines, dielectric layers, and a ferroelectric material layer, featuring a channel pillar surrounded by conductive lines and dielectric layers, allowing for a smaller device size and improved electrical performance through reduced leakage current and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional ferroelectric memory structures are used, then the basic memory function is achieved, but the device size is large and electrical performance is limited
Solution Approach 1:
The patent transitions from a planar memory structure to a three-dimensional structure by forming vertical channel pillars and gate pillars. The channel pillar extends vertically between source and drain regions, while the gate pillar wraps around the channel pillar, creating a vertical stacking architecture that reduces lateral footprint while maintaining functional performance
Solution Approach 2:
The gate pillar is positioned to surround the channel pillar, with the ferroelectric material layer wrapped around the gate pillar. This nested configuration allows the gate control structure to enclose the channel region, maximizing control efficiency within a compact vertical space, thereby reducing device area without compromising electrical characteristics
2Volume of moving object
If device size is reduced, then integration density improves, but leakage current and parasitic capacitance increase
Solution Approach 1:
The patent applies different dielectric materials in specific locations: a first dielectric layer is formed between the channel pillar and surrounding structures, while a second dielectric layer is positioned between the gate pillar and channel pillar. This localized dielectric engineering reduces parasitic capacitance in critical regions without compromising the overall device function, enabling smaller device size with controlled electrical performance
Solution Approach 2:
The ferroelectric material layer acts as an intermediary between the gate pillar and the channel pillar, providing strong electrostatic control over the channel while maintaining electrical isolation. This intermediary layer enables effective gate control in a compact structure, reducing leakage current through the thin-film transistor channel while maintaining small device dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure achieves a smaller device size with enhanced electrical performance, including lower leakage current and parasitic capacitance, and facilitates integration with existing semiconductor manufacturing processes.
Implementation Method 1
a ferroelectric material layer, wherein the first conductive line is located on the substrate, the first dielectric layer is located on the first conductive line, the channel pillar is located on the first conductive line and located in the first dielectric layer, the second conductive line is located on the first dielectric layer and the channel pillar, the gate pillar passes through the second conductive line and located in the channel pillar, the second dielectric layer is located between the gate pillar and the first conductive line, between the gate pillar and the channel pillar, and between the gate pillar and the second conductive line, and the ferroelectric material layer is located between the gate pillar and the second dielectric layer
Data Source
AI summary
A ferroelectric memory structure including a substrate, first and second conductive lines, first and second dielectric layers, a channel pillar, a gate pillar, and a ferroelectric material layer is provided. The first conductive line is located on the substrate. The first dielectric layer is located on the first conductive line. The channel pillar is located on the first conductive line and in the first dielectric layer. The second conductive line is located on the first dielectric layer and the channel pillar. The gate pillar passes through the second conductive line and is located in the channel pillar. The second dielectric layer is located between the gate pillar and the first conductive line, between the gate pillar and the channel pillar, and between the gate pillar and the second conductive line. The ferroelectric material layer is located between the gate pillar and the second dielectric layer.