Ferroelectric Memory Biasing Across Separate Power Domains
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing ferroelectric memory circuits require large voltage biases for operations, leading to increased area consumption and cost due to the need for I/O circuits compatible with both positive and negative voltages, and previous solutions involve costly charge pumps.
Innovation Solution
Implementing a memory system with separate power domains for memory cell operations and logic operations, using lower bias voltages (±1.2 V) for memory cell operations and positive voltages (VDD) for logic, and distributing voltages across word lines, bit lines, and source lines to reduce the voltage range required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large voltage biases are used for memory cell operations, then memory cell switching capability is improved, but area consumption increases due to the need for I/O circuits compatible with both positive and negative voltages
Solution Approach 1:
The patent divides the voltage supply system into separate power domains: a first power domain providing positive and negative voltages (e.g., +1.2V and -1.2V) for memory cell operations, and a second power domain providing only positive voltage (e.g., VDD) for logic operations. This segmentation allows I/O circuits to operate solely in the positive voltage domain, eliminating the need for negative voltage compatibility and reducing the area required for I/O circuits while maintaining the memory cells' ability to switch using bipolar voltages.
2Adaptability or versatility
If charge pumps are used to generate required voltages, then voltage generation capability is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the charge pump functionality from the memory system by providing voltages from external power domains. The first power domain externally provides the positive and negative voltages needed for memory cell operations, and the second power domain externally provides the positive voltage for logic operations. This removal of the charge pump from the memory system reduces device complexity and cost while maintaining the required voltage generation capability through external power supply infrastructure.
3Area of stationary object
If separate power domains are implemented, then area consumption is reduced, but power distribution complexity increases
Solution Approach 1:
The patent implements a dual-power-domain architecture where the first power domain (providing +VDD2 and -VDD2) serves both memory cell operations and provides a reference for voltage generation, while the second power domain (providing VDD) serves logic operations and I/O circuits. The control circuit utilizes voltages from both domains to generate control signals, demonstrating multi-functionality that simplifies the overall power distribution architecture despite the presence of separate power domains.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces area consumption, lowers costs, and improves memory density by eliminating the need for costly I/O circuits and charge pumps, while maintaining compatibility with digital logic domains.
Implementation Method 1
A ferroelectric field-effect transistor (FeFET) is a type of field-effect transistor that includes a ferroelectric material sandwiched between the gate electrode and the source-drain conduction region of the device. Permanent electrical field polarization in the ferroelectric material causes this type of device to retain the transistor's state (biased on or biased off) in the absence of power.
Data Source
AI summary
A memory system including a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a plurality of source lines. The plurality of memory cells are arranged in rows and columns, each of the plurality of memory cells having a gate, a drain, and a source. In the plurality of word lines, each of the word lines having a corresponding row, wherein each of the word lines is coupled to the gates of the memory cells in the corresponding row. In the plurality of bit lines and the plurality of source lines, each of the bit lines and each of the source lines having a corresponding column, where each of the bit lines is connected to the drain of the memory cells in the corresponding column and each of the source lines is connected to the source of the memory cells in the corresponding column. Where, in a write operation, the word line corresponding to a selected memory cell is configured to receive a first voltage, and the bit line and the source line of the selected memory cell are configured to receive a second voltage, and where one of the first voltage or the second voltage is a positive voltage and the other of the first voltage or the second voltage is a negative voltage.