3D Ferroelectric Memory Array Structure for Read-Disturb Retention
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Solution Overview
Problem
Existing memory technologies face challenges in maintaining the polarization state of ferroelectric materials used in memory cells, as reading the memory state can reverse the polarization, requiring immediate rewriting of the cell.
Innovation Solution
A memory array structure with vertically-alternating tiers of insulative material and memory cells, where each memory cell comprises a transistor and a capacitor with a ferroelectric gate insulator, allowing for non-volatile storage by maintaining the polarization state without disturbance during reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If a ferroelectric capacitor is used in a memory cell, then non-volatile storage is achieved, but the act of reading the memory state can reverse the polarization state
Solution Approach 1:
The patent introduces a read-disturb compensation mechanism that acts as an intermediary between the read operation and the ferroelectric capacitor. When a read operation is detected, the system automatically performs a compensating write operation to restore the polarization state if it was reversed during reading. This intermediary compensation step resolves the contradiction by maintaining data integrity without changing the fundamental read mechanism.
Solution Approach 2:
The patent implements a feedback mechanism where the system monitors read operations and uses this information to trigger compensating write operations. The feedback loop detects when polarization state reversal has occurred during reading and automatically corrects it, ensuring that the polarization state remains stable and reliable for data storage purposes.
2Ease of operation
If reading operations are performed on ferroelectric memory cells, then data is retrieved, but immediate rewriting is required to maintain the polarization state
Solution Approach 1:
The patent applies preliminary action by proactively performing compensating write operations immediately after detecting read operations. Rather than waiting for polarization state degradation to occur, the system preemptively restores the state, preventing data loss before it can happen. This eliminates the need for delayed rewriting and maintains continuous data integrity.
Solution Approach 2:
The patent ensures continuity of useful action by making the compensating write operation an automatic, immediate response to read operations. This creates a continuous cycle of read-protect-write that maintains the polarization state without interruption, eliminating gaps where data could be lost and ensuring uninterrupted data retention.
3Reliability
If vertically-alternating tiers of insulative material and memory cells are used, then polarization state is maintained during reading, but device structure becomes more complex
Solution Approach 1:
The patent transitions from a planar memory structure to a three-dimensional vertically-alternating tier structure. By stacking insulative material layers and memory cell layers alternately in the vertical dimension, the design achieves better isolation and protection of the ferroelectric capacitor's polarization state during read operations, while managing the increased structural complexity through systematic layering.
Solution Approach 2:
The patent segments the memory device into distinct alternating layers of insulative material and memory cells. This segmentation creates clear functional zones where insulative layers provide electrical isolation and protection, while memory cell layers contain the active ferroelectric capacitors. The segmented structure manages complexity by dividing the device into repeating, manageable units with specific functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure ensures that the polarization state of ferroelectric materials is maintained, enabling reliable non-volatile storage without the need for immediate rewriting after reading, thereby improving data retention in memory cells.
Implementation Method 1
each memory cell comprises a transistor and a capacitor with a ferroelectric gate insulator, allowing for non-volatile storage by maintaining the polarization state without disturbance during reading
Implementation Method 2
Energy as an electric field may be electrostatically stored within such material
Data Source
AI summary
A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a capacitor. The capacitor comprises a first electrode electrically coupled to a source/drain region of the transistor. The first electrode comprises an annulus in a straight-line horizontal cross-section and a capacitor insulator radially inward of the first electrode annulus. A second electrode is radially inward of the capacitor insulator. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. A sense line is electrically coupled to another source/drain region of multiple of the transistors that are in different memory-cell tiers. Additional embodiments and aspects are disclosed, including methods.