Pinch-Off Ferroelectric Memory Cell Readout Without Depolarization Loss
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Solution Overview
Problem
Existing ferroelectric memory devices suffer from depolarization fields that cause data loss due to high depolarization fields during read operations, leading to reduced retention times and increased power consumption.
Innovation Solution
A pinch-off ferroelectric memory cell connected in series with a select transistor, which maintains the ferroelectric layer in an accumulation state during read operations, eliminating the depolarization field and ensuring long retention times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a classical read-out scheme is applied to a pinch-off ferroelectric FET, then the current can be modulated to distinguish between states, but a depolarization field is introduced that causes the cell to lose its charge during prolonged reading
Solution Approach 1:
The patent inverts the conventional read-out approach by applying a positive gate bias instead of a negative gate bias. This inversion changes the channel state from depletion to accumulation, eliminating the depolarization field that causes charge loss while still enabling current modulation for state distinction through the select transistor configuration
Solution Approach 2:
The patent introduces a select transistor as an intermediary element between the pinch-off ferroelectric FET and the read circuitry. This mediator allows the ferroelectric FET to operate in accumulation mode during reading without directly exposing it to conditions that would create depolarization fields, thus protecting the stored charge while enabling readable output
2Reliability
If floating gate structures or SONOS structures are used to store electrostatic charges, then non-volatile memory functionality is achieved, but high voltages (10-20V) are required that necessitate large charge pumping circuits and high voltage transistors
Solution Approach 1:
The patent changes the voltage parameter from high voltage (10-20V) to low voltage (typically +/-4V or lower) by utilizing the ferroelectric material's remnant polarization property. This parameter change eliminates the need for charge pumping circuits and high voltage transistors, as the ferroelectric layer itself maintains the stored state without requiring external high voltage support structures
Solution Approach 2:
The patent extracts and removes the charge pump circuits and high voltage transistor components from the memory system. By using ferroelectric material with inherent remnant polarization, the design eliminates these auxiliary high-voltage generation components while retaining non-volatile storage functionality
3Power
If the ferroelectric material is used in a FeFET with a silicon channel, then low program/erase voltages are achieved, but a depolarization field is created that works against the polarization and slowly erases the cell
Solution Approach 1:
The patent applies dynamic biasing where the gate voltage is adjusted based on the operational state. During reading, a positive gate bias is applied to maintain accumulation and eliminate depolarization field. During programming/erasing, appropriate voltage pulses are applied. This dynamic approach allows low voltage operation while preventing charge loss during retention periods
Solution Approach 2:
The patent applies a preliminary positive gate bias before reading operations to ensure the channel is in accumulation state. This preliminary action prevents the formation of depolarization field during subsequent read operations, thereby protecting the stored charge from erosion while maintaining low voltage operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides improved retention characteristics, reduced power consumption, and faster programming times without the need for high voltage circuits, making it suitable for low-cost, low-power non-volatile memory applications.
Implementation Method 1
the gate oxide dielectric is replaced by a ferroelectric material for a FeFET memory device... These states correspond to the so-called remnant polarization states +Pr and -Pr, respectively
Implementation Method 2
The pinch-off FET comprises a relatively highly doped n-type semiconductor channel on a n-type substrate, which will remain in accumulation even in the retention condition when no voltage is applied
Implementation Method 3
Reading is then performed by sensing the current through a channel which is modulated by this stored charge
Data Source
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AI summary
A non-volatile memory cell (200) is disclosed comprising a pinch-off ferroelectric memory FET (40) and at least one select device (80), said at least one select device (80) being electrically connected in series to the pinch-off ferroelectric memory FET (40).