Ferroelectric Memory Cell Layout With Shared Capacitors for Higher Density
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Solution Overview
Problem
Conventional ferroelectric memory structures face limitations in scaling down beyond 14 nm, leading to high area, high cost, and high power consumption, while existing solutions struggle to increase storage capacity and reduce memory cell size effectively.
Innovation Solution
A ferroelectric memory design incorporating a gate-all-around transistor with integrated ferroelectric capacitors, allowing multiple memory cells to be integrated on a single transistor, and utilizing shared connections and stacking configurations to enhance density and reduce area, while maintaining low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 1T1C structure is used, then high durability and low operating voltage are achieved, but scale-down capability is limited and area is large
Solution Approach 1:
Multiple ferroelectric capacitors are merged under a single transistor gate, with multiple capacitors sharing one transistor control. This integration reduces the number of transistors required per memory cell, thereby decreasing the overall memory cell area while maintaining the necessary read/write functionality through shared control signals.
Solution Approach 2:
The patent transitions from planar capacitor arrangements to three-dimensional stacked configurations, where ferroelectric capacitors are stacked vertically in multiple layers. This vertical stacking enables higher density by utilizing the third dimension (height) rather than only horizontal expansion, significantly reducing the footprint area of each memory cell.
2Quantity of substance
If DRAM scaling is continued, then storage capacity requirement is met, but area increases, cost increases, and power consumption increases
Solution Approach 1:
The patent employs multi-layer stacked architectures where memory cells are arranged in vertical columns spanning multiple layers. This three-dimensional organization allows exponential growth in storage capacity (2^N for N layers) without proportional increases in planar area, as each additional layer adds capacity while sharing the same footprint with lower layers.
Solution Approach 2:
The invention creates a universal memory cell design that can operate in different configurations (1T1C, 1T2C, 1T4C, etc.) by varying the number of capacitors per transistor. This multi-functional architecture adapts to different storage capacity requirements without changing the fundamental cell structure, allowing scalable capacity expansion without area penalty.
3Use of energy by stationary object
If conventional ferroelectric capacitor structure is used, then low power consumption is achieved, but density is low and area is large
Solution Approach 1:
Multiple ferroelectric capacitors are combined under a single transistor, sharing the same control gate and read/write circuitry. This merging reduces the total transistor count and associated overhead circuitry, increasing cell density while maintaining the low-power characteristics of ferroelectric materials, as each capacitor still benefits from the non-volatile polarization state.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design significantly increases memory cell density, reduces area, and improves scalability, while maintaining fast reading/writing speeds and low power consumption, facilitating efficient integration with existing memory technologies.
Implementation Method 1
a ferroelectric random access memory (ferroelectric memory) is a type of memory made according to a principle that a polarization direction of a ferroelectric material changes under an action of an electric field
Data Source
AI summary
Example ferroelectric memories and storage devices are described. One example ferroelectric memory includes at least one bit cell. A bit cell in the at least one bit cell includes a plurality of ferroelectric capacitors and a first transistor. The first transistor includes a first gate, a first channel, a first source, and a first drain. The first source and the first drain are located at two ends of the first channel. One electrode of each of the plurality of ferroelectric capacitors is formed on the first gate.