3D Memory Device Ferroelectric Sidewall Lining Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, integration density increases, but this leads to new challenges such as parasitic capacitance and energy consumption bottlenecks, particularly in three-dimensional memory devices, which require innovative solutions to maintain performance and efficiency.
Innovation Solution
The method involves forming a three-dimensional memory device with a ferroelectric material, where a first and second layer stack are created over a substrate, with inner spacers and ferroelectric material lining the sidewalls of openings, and gate electrodes filled with conductive material, followed by a recess filled with dielectric material, reducing parasitic capacitance and enhancing memory cell efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but parasitic capacitance and energy consumption increase
Solution Approach 1:
The memory device is divided into multiple layer stacks (first layer stack, second layer stack) with distinct functional regions. Each layer stack contains separated source/drain regions, channel regions, and gate electrodes, allowing independent optimization of each segment to reduce parasitic capacitance while maintaining high integration density through vertical stacking
Solution Approach 2:
The patent transitions from planar two-dimensional memory structures to three-dimensional vertical stacking. Multiple layer stacks are stacked vertically over the substrate, with gate electrodes extending through multiple layers. This vertical dimension allows significantly higher integration density without increasing the lateral footprint, thereby avoiding the parasitic capacitance issues that would result from further lateral scaling
2Quantity of substance
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but energy consumption increases
Solution Approach 1:
The memory device segments storage functionality across multiple layer stacks with distinct source/drain and channel regions. This segmentation allows selective activation of specific memory cells and reduces the capacitive load that must be charged/discharged during operations, thereby lowering energy consumption while maintaining high integration density
Solution Approach 2:
By moving to three-dimensional vertical stacking, the patent achieves high integration density without further reducing lateral feature sizes. This prevents the exponential increase in parasitic capacitance and short-channel effects that would otherwise cause energy consumption to skyrocket, thus decoupling density improvements from energy penalties
3Quantity of substance
If three-dimensional memory structure is implemented to increase integration density, then more components can be integrated, but parasitic capacitance increases
Solution Approach 1:
The patent applies different material properties and structural configurations to different regions within the three-dimensional memory device. Inner spacers with specific dielectric properties are placed in contact with source/drain regions, while ferroelectric materials are positioned in specific locations to reduce parasitic capacitance. This local optimization of material and structure properties mitigates parasitic capacitance effects while maintaining the benefits of three-dimensional stacking
Solution Approach 2:
Inner spacers are introduced as intermediary structures between the source/drain regions and the ferroelectric material. These spacers act as dielectric mediators that reduce direct capacitive coupling between conductive elements, thereby lowering parasitic capacitance in the three-dimensional memory structure while maintaining electrical connectivity and device functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for high-density memory arrays with reduced parasitic capacitance and energy consumption, enabling faster, smaller, and more cost-effective semiconductor devices, particularly suitable for emerging applications like IoT and machine learning.
Implementation Method 1
lining sidewalls of the array of openings with a ferroelectric material
Data Source
AI summary
A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.