Ferroelectric Memory Stack Using Antiferroelectric Layers
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Solution Overview
Problem
Current ferroelectric memory devices face challenges in achieving high bit densities and minimizing program disturb due to interference between memory cells, and they require optimization for smaller node integration.
Innovation Solution
A three-dimensional ferroelectric memory device is developed, incorporating an alternating stack of insulating and conductive layers with transition metal nitride liners and conductive fill materials, featuring ferroelectric and antiferroelectric layers to enhance coercive voltage and polarization switching, while decoupling ferroelectric properties between cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ferroelectric memory devices are used, then they can store information using ferroelectric material polarization, but they suffer from cell-to-cell interference and program disturb due to interference between memory cells
Solution Approach 1:
An antiferroelectric layer is introduced as an intermediary between the ferroelectric memory layers. This antiferroelectric layer acts as a mediator that blocks electric field penetration between adjacent memory cells, thereby preventing cell-to-cell interference and program disturb while allowing the ferroelectric material to maintain its information storage function.
Solution Approach 2:
The memory device uses a composite structure combining ferroelectric and antiferroelectric materials in alternating layers. This composite material approach leverages the polarization properties of ferroelectric materials for data storage while utilizing the blocking properties of antiferroelectric materials to isolate adjacent cells, resolving the interference problem.
2Productivity
If bit density is increased to achieve higher storage capacity, then memory cell size must be reduced, but this leads to increased interference between adjacent cells
Solution Approach 1:
The patent transitions from planar memory cell arrangement to a vertical stacked configuration with alternating ferroelectric and antiferroelectric layers. This dimensional change allows higher bit density in the vertical direction while the antiferroelectric layers provide natural isolation between cells in the vertical stack, reducing interference as cells are packed more densely.
3Area of stationary object
If isolation layers are made thinner to reduce device footprint, then integration density improves, but ferroelectric properties between cells become coupled and interfere with each other
Solution Approach 1:
The antiferroelectric layer serves as an effective intermediary that provides electrical isolation between adjacent ferroelectric memory cells. Even when isolation layers are made thin to reduce footprint, the antiferroelectric material maintains proper ferroelectric property isolation by blocking electric field coupling between cells.
4Productivity
If ferroelectric memory devices are scaled to smaller nodes, then higher density is achieved, but manufacturing precision and control become more difficult
Solution Approach 1:
The patent combines the formation of ferroelectric and antiferroelectric layers into a unified alternating stack structure that can be manufactured together in a single integrated process. This merging of layer formation steps simplifies scaling to smaller nodes by reducing the number of separate manufacturing operations required, thereby improving manufacturing precision and control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces cell-to-cell interference, allows for thinner isolation layers, and achieves higher bit densities with improved programming windows and reduced program disturb, facilitating easier integration and scaling to smaller nodes.
Implementation Method 1
A ferroelectric material refers to a material that displays spontaneous polarization of electrical charges in the absence of an applied electric field. The net polarization P of electrical charges within the ferroelectric material is non-zero in the minimum energy state.
Implementation Method 2
Polarization P of a ferroelectric material as a function of an applied voltage V thereacross displays hysteresis.
Implementation Method 3
incorporating an alternating stack of insulating and conductive layers with transition metal nitride liners and conductive fill materials, featuring ferroelectric and antiferroelectric layers to enhance coercive voltage and polarization switching, while decoupling ferroelectric properties between cells
Data Source
AI summary
A ferroelectric memory device includes a semiconductor channel, a gate electrode, and a ferroelectric memory element located between the semiconductor channel and the gate electrode. The ferroelectric memory element includes at least one ferroelectric material portion and at least one antiferroelectric material portion.