3D Ferroelectric Memory String With Metal Channel Reliability
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Solution Overview
Problem
The integration degree of semiconductor devices is limited by the area occupied by unit memory cells, and there is a need for improved operation reliability in three-dimensional semiconductor devices.
Innovation Solution
A semiconductor device with a gate structure comprising alternately stacked conductive and insulating layers, a metal channel layer, a first semiconductor channel layer, and a ferroelectric layer, along with bit lines, memory strings, and transistors, is designed to enhance integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If memory cells are stacked in three dimensions to improve integration degree, then the area occupied by unit memory cells is reduced, but the operation reliability becomes more difficult to maintain
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell layout to three-dimensional stacked memory cells. Multiple memory cells are vertically stacked along the channel length direction, with gate structures positioned at different heights. This dimensional change reduces the footprint area of each memory cell while maintaining functional integrity through the stacked configuration.
Solution Approach 2:
The memory cell is divided into segmented components: metal channel layers at different heights, semiconductor channel layers, gate structures, and insulating layers. Each segment serves a specific function, and the segmented structure allows independent optimization of each component while maintaining overall reliability in the three-dimensional stacked configuration.
2Speed
If metal channel layers are used to improve carrier mobility and operation speed, then the operation reliability becomes more difficult to control
Solution Approach 1:
The patent employs composite material structures combining metal channel layers with semiconductor channel layers and ferroelectric layers. The metal channel layer provides high carrier mobility for fast operation, while the semiconductor channel layer and ferroelectric layer offer controllable electrical characteristics and non-volatile memory functionality. This composite approach balances speed and reliability by leveraging the complementary properties of different materials.
Solution Approach 2:
The patent controls the electrical parameters of the metal channel layer through adjustment of layer thickness, material composition, and interface characteristics. By optimizing these parameters, the patent achieves desired carrier mobility for high-speed operation while maintaining reliability through controlled electrical behavior in the three-dimensional stacked structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution increases memory integration and improves operation speed by using metal channel layers with high carrier mobility, enabling efficient distinction and operation of selected and unselected memory strings.
Implementation Method 1
a ferroelectric layer surrounding the metal channel layer and the first semiconductor channel layer
Data Source
AI summary
A semiconductor device may include a gate structure including conductive layers and insulating layers alternately stacked, a metal channel layer extending through the gate structure, a first semiconductor channel layer extending through the gate structure and connecting to the metal channel layer, and a ferroelectric layer surrounding the metal channel layer and the first semiconductor channel layer.