Ferroelectric Multiplier Cells With Fewer Transistors and Interconnects
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Solution Overview
Problem
Existing multiplier cells in CMOS logic consume high power and occupy large area due to the increasing number of transistors, which poses challenges for reducing power consumption and increasing efficiency.
Innovation Solution
The use of ferroelectric or paraelectric materials in the design of multiplier cells, specifically in the implementation of 1-bit full adders and AND gates, which incorporate majority and minority gates with non-linear polar material, reducing the need for switching transistors and minimizing interconnect routings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If traditional CMOS logic gates (AND, OR, XOR) are used to build multiplier cells, then the circuit can perform multiplication operations, but the number of transistors increases leading to high power consumption and large area occupation
Solution Approach 1:
The patent replaces the mechanical transistor-based logic gate system with a field-based computational system using non-linear polar materials. Instead of using multiple transistors to implement AND, OR, and XOR gates, the invention uses the non-linear polarization response of ferroelectric or paraelectric materials to directly compute multiplication results through field interactions, eliminating the need for complex transistor networks.
Solution Approach 2:
The patent changes the fundamental operating parameter from transistor switching states to the polarization state of non-linear polar materials. By utilizing the non-linear relationship between electric field and polarization in ferroelectric or paraelectric materials, the system achieves computational functionality with fewer physical components, directly reducing power consumption and area.
2Productivity
If the number of transistors in multiplier cells is increased to achieve desired computational functionality, then the multiplication operation can be performed, but the area occupied by the circuit increases
Solution Approach 1:
The patent replaces the mechanical transistor-based logic gate system with a field-based computational system using non-linear polar materials. Instead of using multiple transistors to implement AND, OR, and XOR gates, the invention uses the non-linear polarization response of ferroelectric or paraelectric materials to directly compute multiplication results through field interactions, eliminating the need for complex transistor networks.
Solution Approach 2:
The non-linear polar material structure serves multiple computational functions simultaneously. The same material region performs the functions of AND gates, OR gates, and XOR gates through different field configurations and polarization states, eliminating the need for separate dedicated circuit areas for each logic operation.
3Adaptability or versatility
If more transistors are used in the multiplier cell design, then the circuit can handle complex multiplication operations, but the interconnect routing length and complexity increase
Solution Approach 1:
The patent replaces the mechanical transistor-based logic gate system with a field-based computational system using non-linear polar materials. Instead of using multiple transistors to implement AND, OR, and XOR gates, the invention uses the non-linear polarization response of ferroelectric or paraelectric materials to directly compute multiplication results through field interactions, eliminating the need for complex transistor networks.
Solution Approach 2:
The patent merges the functions of multiple logic gates (AND, OR, XOR) and their interconnect routing into a single integrated non-linear polar material structure. The computational operations and data pathways are combined within the same material region, eliminating the need for extensive external interconnect routing between separate gate components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in significantly reduced power consumption and area, with the ferroelectric or paraelectric based multiplier cells achieving 10 times fewer interconnect lengths compared to traditional CMOS circuits, while also enabling intermittent operation with zero power drain.
Implementation Method 1
The use of ferroelectric or paraelectric materials in the design of multiplier cells, specifically in the implementation of 1-bit full adders and AND gates, which incorporate majority and minority gates with non-linear polar material
Implementation Method 2
The use of ferroelectric or paraelectric materials in the design of multiplier cells, specifically in the implementation of 1-bit full adders and AND gates, which incorporate majority and minority gates with non-linear polar material
Data Source
AI summary
A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and/or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.