Ferroelectric Multiplier Array With Fewer Transistors and Lower Power
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Solution Overview
Problem
Existing multiplier cell architectures in CMOS logic face challenges in reducing power consumption and area due to the increasing number of transistors required, which hinders the goal of lower power consumption and more efficient battery usage.
Innovation Solution
The use of ferroelectric or paraelectric materials in the design of multiplier cells, specifically in the implementation of 1-bit full adders and AND gates, which are derived from majority and minority gates, reduces the number of transistors and interconnects, thereby lowering power consumption and area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional CMOS logic gates (AND gate, OR gate, XOR gates) are used in multiplier cells, then the circuit can perform multiplication operations, but the number of transistors increases, leading to increased power consumption and area
Solution Approach 1:
The patent changes the fundamental operating parameters by replacing voltage-based CMOS logic with charge-based floating gate transistor logic. This parameter change enables the circuit to perform the same multiplication function with dramatically reduced power consumption, as the floating gate transistors can maintain their state without continuous power supply, unlike traditional CMOS gates that require constant voltage to maintain logic states.
Solution Approach 2:
The patent substitutes the electrical field-based CMOS logic mechanism with a charge storage-based floating gate mechanism. Instead of using voltage levels to represent logic states in CMOS, the invention uses trapped charge on floating gates to represent binary states, fundamentally changing the physical mechanism from electrical field control to charge storage, which enables ultra-low power operation.
2Productivity
If traditional CMOS logic gates are used in multiplier cells, then the circuit can perform multiplication operations, but the number of transistors increases, leading to increased area
Solution Approach 1:
The patent changes the fundamental operating parameters by replacing voltage-based CMOS logic with charge-based floating gate transistor logic. This parameter change enables the circuit to perform the same multiplication function with dramatically reduced power consumption, as the floating gate transistors can maintain their state without continuous power supply, unlike traditional CMOS gates that require constant voltage to maintain logic states.
Solution Approach 2:
The patent substitutes the electrical field-based CMOS logic mechanism with a charge storage-based floating gate mechanism. Instead of using voltage levels to represent logic states in CMOS, the invention uses trapped charge on floating gates to represent binary states, fundamentally changing the physical mechanism from electrical field control to charge storage, which enables ultra-low power operation.
3Use of energy by moving object
If the number of transistors is reduced to lower power consumption, then power consumption decreases, but the ability to perform multiplication operations may be compromised
Solution Approach 1:
The patent extracts and eliminates unnecessary transistors from the traditional multiplier cell architecture. By using floating gate transistors that can perform logic functions with fewer components, the invention removes redundant transistors while maintaining the full multiplication capability through the inherent charge-storage logic mechanism of floating gate devices.
Solution Approach 2:
The floating gate transistor serves multiple functions simultaneously - it acts as both a storage element and a logic gate component. A single floating gate transistor can represent a binary state and participate in logic operations, eliminating the need for separate storage and logic components required in traditional CMOS designs, thus maintaining functionality with reduced transistor count.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integration of non-linear polar materials in the logic gates results in extremely compact multiplier circuitry with significantly reduced power consumption, achieving 10× fewer interconnect length compared to traditional CMOS circuits, and allowing for intermittent operation with zero power drain when not in use.
Implementation Method 1
The AND gate comprises a first capacitor to receive the multiplicand, wherein the first capacitor includes non-linear polar material; a second capacitor to receive the multiplier, wherein the second capacitor includes non-linear polar material
Data Source
AI summary
A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and/or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.