Ferroelectric Neuromorphic Circuit for In-Memory Computing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The Von Neumann computing architecture is limited in processing speed and energy efficiency for large data sets due to the separation of main memory and arithmetic logic units, leading to inefficiencies in data transfer and processing.
Innovation Solution
The development of semiconductor devices and neuromorphic circuits utilizing ferroelectric materials, which include transistors with gate insulating films made of ferroelectric materials, enabling parallel processing and efficient data storage and processing in neuromorphic computing apparatuses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If main memory and arithmetic logic units are separated in Von Neumann architecture, then data storage capacity is improved, but data transfer efficiency deteriorates
Solution Approach 1:
The patent merges memory and computing functions by implementing in-memory computing architecture where computation operations are performed directly within the memory array, eliminating the need for data transfer between separate memory and processing units. This resolves the bottleneck caused by spatial separation of memory and arithmetic logic units.
Solution Approach 2:
The patent transitions from traditional planar transistor arrangements to vertically stacked three-dimensional transistor structures, enabling increased storage density without proportionally increasing the footprint area. This dimensional change allows more memory cells to be packed into the same space while maintaining efficient access pathways.
2Productivity
If data capacity to be processed increases, then computing power is improved, but power consumption increases
Solution Approach 1:
By combining memory and processing functions into a single integrated structure, the patent eliminates redundant data transfer operations that consume significant power. Computation is performed in-place within the memory array, reducing the energy required to move large datasets between separate components.
Solution Approach 2:
The patent implements local computation capabilities within specific regions of the memory array, allowing data processing to occur closer to where the data is stored. This reduces the distance data must be transported and minimizes the power consumption associated with long-distance data movement across the chip.
3Quantity of substance
If traditional RRAM and PCM technologies are used, then data storage is achieved, but processing accuracy deteriorates
Solution Approach 1:
The patent employs composite material structures in the memory devices that combine multiple functional layers with distinct properties, enabling both reliable data storage and high-precision computation. The composite structure allows separate optimization of storage durability and computational accuracy within the same device architecture.
Solution Approach 2:
The patent utilizes controllable parameter changes in the memory device characteristics, such as resistance states and threshold voltages, to represent and manipulate data with high precision. By carefully controlling these physical parameters during write and read operations, the system achieves accurate computation results while maintaining robust data storage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves data processing speed and reduces power consumption, achieving high accuracy in image recognition tasks, such as identifying the MNIST data set with a high probability of about 97.3%, compared to traditional RRAM and PCM technologies.
Implementation Method 1
The gate insulating film includes a ferroelectric material
Data Source
AI summary
A semiconductor device includes a first transistor including a first channel layer of a first conductivity type, a second transistor provided in parallel with the first transistor and including a second channel layer of a second conductivity type, and a third transistor stacked on the first and second transistors. The third transistor may include a gate insulating film including a ferroelectric material. The third transistor may include third channel layer and a gate electrode that are spaced apart from each other in a thickness direction with the gate insulating film therebetween.