Ferroelectric Pillar Capacitor Structure for Low-Voltage Dense Memory
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Solution Overview
Problem
Conventional non-volatile memories, such as MRAM, NAND, or NOR flash, are not suitable for low-power and compact computing devices due to high write energy, low density, and high power consumption.
Innovation Solution
A ferroelectric pillar capacitor is integrated with a transistor in a 1T-1C configuration, allowing for low voltage switching and higher density memory operation by using a U-shaped structure with multiple electrode layers, enabling non-volatility and efficient energy use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional non-volatile memories (MRAM, NAND, NOR flash) are used, then non-volatility is achieved, but power consumption and write energy are high
Solution Approach 1:
The capacitor electrode is divided into multiple segments (first bottom electrode, second bottom electrode, top electrode) separated by dielectric layers, allowing independent optimization of each segment's function to reduce overall power consumption while maintaining data retention
Solution Approach 2:
The patent uses composite capacitor structures combining different dielectric materials (first dielectric, second dielectric, third dielectric) with distinct properties to achieve low power consumption and high reliability simultaneously through material property optimization
2Quantity of substance
If conventional memory structures are used, then manufacturing is simpler, but memory density is low
Solution Approach 1:
The capacitor structure transitions from planar to three-dimensional by stacking multiple electrodes and dielectric layers vertically, increasing storage capacity per unit area and achieving higher memory density through vertical space utilization
Solution Approach 2:
Multiple capacitor elements are nested within each other through shared electrodes (the second bottom electrode serves as both a bottom electrode for one capacitor and a top electrode for another), increasing density without proportionally increasing manufacturing complexity
3Power
If conventional capacitor structures are used, then manufacturing is easier, but switching voltage is high
Solution Approach 1:
The patent optimizes physical parameters including dielectric layer thicknesses (first, second, and third dielectrics) and electrode dimensions to reduce the voltage required for switching while maintaining manufacturability through standardized fabrication processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ferroelectric pillar capacitor enables low voltage switching and higher density memory with reduced power consumption, allowing for more bit-cells per die while maintaining non-volatility, addressing the limitations of traditional memory technologies.
Implementation Method 1
A ferroelectric pillar capacitor is integrated with a transistor in a 1T-1C configuration, allowing for low voltage switching and higher density memory operation
Data Source
AI summary
The memory bit-cell formed using the ferroelectric capacitor results in a taller and narrower bit-cell compared to traditional memory bit-cells. As such, more bit-cells can be packed in a die resulting in a higher density memory that can operate at lower voltages than traditional memories while providing the much sought after non-volatility behavior. The pillar capacitor includes a plug that assists in fabricating a narrow pillar.