Ferroelectric Stack Memory Structure for Scaled Memory Window Control
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Solution Overview
Problem
The challenge of forming reliable semiconductor devices at smaller sizes is exacerbated by the difficulty in fabricating complex circuits with decreasing feature sizes, which affects the performance and reliability of memory devices.
Innovation Solution
A memory device structure incorporating a ferroelectric stack with a thin dielectric layer between two ferroelectric layers, enhancing memory window performance by optimizing the thicknesses of the ferroelectric layers and using a semiconductor nanostructure such as a nanowire or nanosheet.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of ferroelectric layers is increased to maintain ferroelectricity, then memory device reliability is improved, but device geometric size increases
Solution Approach 1:
The patent employs a composite ferroelectric stack structure consisting of multiple ferroelectric layers (first and second ferroelectric layers) separated by a dielectric layer. This composite arrangement allows the system to maintain ferroelectricity and achieve reliable memory operation without requiring each individual ferroelectric layer to be thick, thus resolving the contradiction between reliability and geometric size.
Solution Approach 2:
The ferroelectric function is segmented across multiple thin layers rather than achieved through a single thick layer. The first ferroelectric layer and second ferroelectric layer are separated by a dielectric layer, allowing each layer to be thin while collectively providing the necessary ferroelectric properties for reliable memory operation.
2Productivity
If feature sizes are decreased to increase functional density, then production efficiency is improved, but manufacturing difficulty increases
Solution Approach 1:
The patent transitions from a planar memory structure to a three-dimensional vertical structure with stacked ferroelectric layers. This dimensional change allows increased functional density without proportionally decreasing feature sizes, thereby maintaining manufacturing feasibility while improving production efficiency.
Solution Approach 2:
The dielectric layer is nested between the first and second ferroelectric layers, creating a compact stacked arrangement. This nested structure enables multiple functional layers to occupy a smaller footprint, increasing functional density while avoiding the need for extremely small feature sizes that would complicate manufacturing.
3Reliability
If a thin dielectric layer is inserted between ferroelectric layers to optimize memory window, then memory device performance is improved, but device complexity increases
Solution Approach 1:
A dielectric layer is introduced as an intermediary between the first and second ferroelectric layers. This intermediate layer optimizes the memory window by controlling the electric field distribution and polarization characteristics, thereby improving memory device performance while adding only moderate structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves memory device performance by maintaining ferroelectricity and enhancing memory window without increasing the thickness of each ferroelectric layer, thereby addressing the challenges of scaling down in semiconductor manufacturing.
Implementation Method 1
A memory device structure incorporating a ferroelectric stack with a thin dielectric layer between two ferroelectric layers, enhancing memory window performance by optimizing the thicknesses of the ferroelectric layers
Data Source
AI summary
A method includes forming a semiconductor layer over a substrate; depositing a first ferroelectric layer over a channel region of the semiconductor layer, depositing a first dielectric layer over the first ferroelectric layer; depositing a second ferroelectric layer over the first dielectric layer, depositing a gate metal layer over the second ferroelectric layer; patterning the gate metal layer, the second ferroelectric layer, the first dielectric layer, and the first ferroelectric layer to form a gate structure; and forming source/drain regions in the semiconductor layer and on opposite sides of the gate structure.