Ferroelectric Transistor Stack for Linear Multi-Level Memory
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Solution Overview
Problem
Conventional ferroelectric transistors face challenges in implementing multi-level characteristics due to a limited memory window defined by the characteristics of the ferroelectric layer, and existing methods like incremental step pulse programming struggle to achieve linear multi-level characteristics because polarization changes rapidly in the coercive electric field.
Innovation Solution
A ferroelectric transistor design with specific capacitance ratios and layer configurations, including a substrate, control gate electrode, and multiple ferroelectric layers, allows for a memory window expansion and enables linear multi-level characteristics by controlling displacement currents through an inner electrode layer using a current control device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional ferroelectric transistor structure is used, then device simplicity is maintained, but memory window is limited and multi-level characteristics cannot be implemented
Solution Approach 1:
The patent implements a nested capacitor structure where an inner electrode layer is positioned between the control gate electrode and the semiconductor channel layer, with first and second ferroelectric layers surrounding it. This nested configuration enables multi-level memory characteristics by creating two stacked capacitor structures (first stacked structure with control gate, inner electrode, and first ferroelectric layer; second stacked structure with inner electrode, second ferroelectric layer, and semiconductor channel) without fundamentally changing the basic transistor architecture.
Solution Approach 2:
The patent transitions from a conventional single-layer ferroelectric structure to a stacked multi-layer structure by adding the inner electrode layer and multiple ferroelectric layers in the vertical dimension. This dimensional change creates two distinct capacitor structures stacked together, enabling expanded memory window and multi-level characteristics while maintaining planar device footprint.
2Manufacturing precision
If incremental step pulse programming method is used, then programming capability is achieved, but linear multi-level characteristics cannot be implemented due to rapid polarization changes in coercive electric field
Solution Approach 1:
The patent utilizes parameter changes in the capacitance ratio between the first and second stacked structures to achieve linear multi-level characteristics. By controlling the ratio of second capacitance (C2) to first capacitance (C1) to be 5 or more, the patent enables precise control over polarization states and achieves linear voltage distribution across multiple memory levels, overcoming the non-linear behavior caused by rapid polarization changes in the coercive electric field.
3Reliability
If capacitance ratio of stacked structures is increased, then memory window is expanded, but device fabrication precision requirements increase
Solution Approach 1:
The patent achieves a capacitance ratio (C2/C1) of 5 or more by optimizing the thickness and area parameters of the ferroelectric layers and electrode structures. Specifically, the first ferroelectric layer thickness is controlled to be greater than the second ferroelectric layer thickness, and the area of the control gate electrode is optimized relative to the inner electrode layer, enabling expanded memory window (7V or more) while maintaining manufacturability through parameter optimization rather than extreme precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances memory window performance, improves operating reliability, and increases memory capacity by enabling high-order multi-level operations and stable polarization control.
Implementation Method 1
a first ferroelectric layer on the control gate electrode layer, an inner electrode layer on the first ferroelectric layer, a second ferroelectric layer on the inner electrode layer
Implementation Method 2
a ratio of a second capacitance of a second stacked structure of the inner electrode layer, the second ferroelectric layer, and the semiconductor channel layer to a first capacitance of a first stacked structure of the control gate electrode layer, the first ferroelectric layer, and the inner electrode layer is 5 or more
Data Source
AI summary
A ferroelectric transistor according to an aspect of the present disclosure includes a substrate, a control gate electrode layer formed on the substrate, a first ferroelectric layer on the control gate electrode layer, an inner electrode layer on the first ferroelectric layer, a second ferroelectric layer on the inner electrode layer, and a semiconductor channel layer on the second ferroelectric layer, wherein a ratio of a second capacitance of a second stacked structure of the inner electrode layer, the second ferroelectric layer, and the semiconductor channel layer to a first capacitance of a first stacked structure of the control gate electrode layer, the first ferroelectric layer, and the inner electrode layer is 5 or more.