3D Ferroelectric Transistor Structure With Fewer Process Steps
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Solution Overview
Problem
The challenge in semiconductor device fabrication lies in the limitations of forming fine patterns due to resolution constraints, which hinders the integration of three-dimensional semiconductor devices, particularly in reducing the number of processes and improving resistance characteristics of three-dimensionally arranged ferroelectric field effect transistors.
Innovation Solution
A semiconductor device is fabricated with a substrate having a cell region and extension region, featuring alternately stacked insulating layers, conductive lines, a ferroelectric layer, and a semiconductor layer, where the number of processes is reduced by forming a stacked structure with sacrificial layers and trenches, and the resistance characteristics are enhanced through the use of a ferroelectric layer and semiconductor layer configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If design rule is reduced to increase integration density, then area occupied by unit cell is reduced, but forming fine patterns becomes limited due to resolution constraints
Solution Approach 1:
The patent transitions from two-dimensional planar device arrangement to three-dimensional vertical stacking, where multiple insulating layers and conductive elements are stacked in the third direction (vertical direction) to achieve higher integration density without reducing the lateral area of unit cells, thereby avoiding fine pattern formation limitations
2Productivity
If three-dimensional semiconductor devices are implemented to overcome resolution limitations, then integration density is improved, but the number of fabrication processes increases
Solution Approach 1:
The patent forms a stacked structure comprising alternating insulating layers and sacrificial layers in advance before forming the final device structure. This preliminary stacking enables subsequent trench formation and conductive line deposition to proceed more efficiently, reducing the total number of fabrication processes required for three-dimensional device implementation
Solution Approach 2:
The patent introduces sacrificial layers as intermediary structures that facilitate the formation of the three-dimensional device architecture. These sacrificial layers are temporarily formed between insulating layers to enable trench formation and conductive line deposition, and are subsequently removed to complete the device structure, thereby simplifying the overall fabrication process
3Reliability
If three-dimensional ferroelectric field effect transistors are fabricated, then device functionality is achieved, but resistance characteristics deteriorate
Solution Approach 1:
The patent forms conductive lines with different structures in different regions: first conductive lines extend in the first direction with specific patterns, while second conductive lines extend in the third direction. This localized differentiation of conductive line structures optimizes resistance characteristics in different regions of the three-dimensional device while maintaining overall functionality
Solution Approach 2:
The patent varies the structural parameters of conductive lines, including their extension directions, spacing, and cross-sectional areas, to optimize resistance characteristics. By adjusting these geometric parameters of the conductive pathways in the three-dimensional structure, the device achieves improved electrical performance while maintaining ferroelectric field effect transistor functionality
Data Source
AI summary
A semiconductor device comprises a substrate that extends in first and second directions and includes a cell region and an extension region that extends from the cell region in the first direction, first and second insulating layers alternately stacked on the substrate in a third direction, a conductive line disposed on one sidewall of the second insulating layer in the second direction, a conductive pillar that extends in the third direction and penetrates through the first insulating layer, a semiconductor layer disposed on one sidewall of the conductive pillar and that extends in the third direction, and a ferroelectric layer disposed between the conductive line and the semiconductor layer and that extends in the third direction. The conductive line includes first and second conductive patterns spaced apart from each other in the second direction, and the second insulating layer is disposed between the first and second conductive patterns.