FET Gate Stress Testing via Common Test Line
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Solution Overview
Problem
Testing operational reliability of field-effect transistors (FETs) in devices with a large number of cells is cumbersome and costly due to limited space and close proximity of cells, making front-end gate stress tests challenging, and back-end testing expensive as failing current sources cannot be filtered out early in production.
Innovation Solution
A device with a common power line and common test line, where each cell includes a FET with switches controlled by a controller to apply stress voltage to both source and drain contacts, allowing for parallel or serial execution of gate stress tests, reducing testing time and top routing requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If individually contacting each cell for gate stress testing is performed, then measurement precision of leakage currents is improved, but device complexity and ease of operation deteriorate due to cumbersome testing procedures
Solution Approach 1:
Multiple individual cell contacts are merged into a single common test line that can simultaneously contact multiple cells. The patent implements this by connecting multiple cell drains to a shared test line, allowing parallel stress testing of multiple FETs through one contact point, thereby simplifying the testing procedure while maintaining measurement capability.
Solution Approach 2:
The common test line serves multiple functions: it acts as a stress voltage application path, a leakage current measurement path, and a universal contact interface for multiple cells. This multi-functional design eliminates the need for separate individual contacts for each cell, improving ease of operation without sacrificing measurement precision.
2Productivity
If front-end gate stress testing is performed, then productivity is improved by early detection of defective devices, but device complexity increases due to space constraints and close proximity of cells
Solution Approach 1:
The patent merges multiple test functions into a compact common test line structure that fits within the limited space of closely-spaced cells. By combining multiple drain contacts into a single shared test line, the physical complexity is reduced while enabling comprehensive front-end testing of multiple cells simultaneously.
Solution Approach 2:
The common test line provides universal access to multiple cells through a single structure, eliminating the need for complex individual routing for each cell. This multi-functional approach allows front-end testing to be performed with minimal additional device complexity, as the same test line serves all cells in the array.
3Reliability
If back-end gate stress testing is performed, then reliability is improved by testing after final assembly, but loss of time increases due to inability to filter out failing current sources early
Solution Approach 1:
The patent enables preliminary gate stress testing to be performed at the front-end before final device assembly. By implementing the common test line structure that allows early testing, defective FETs can be identified and filtered out during manufacturing, preventing them from reaching final assembly and reducing rework time later in the production cycle.
4Ease of operation
If common power line and common test line are used, then ease of operation is improved by simplifying voltage application, but measurement precision may deteriorate due to potential interference between multiple cells
Solution Approach 1:
While using a common test line for ease of operation, the patent applies segmentation by individually controlling the gate voltages of each FET through separate gate lines. This allows selective activation and measurement of individual cells, preventing interference between simultaneously tested cells and maintaining measurement precision despite the shared test line.
Solution Approach 2:
The patent implements local quality by providing individual gate control for each cell while sharing the test line. Each cell can be independently configured with appropriate gate voltage to enable or disable testing, ensuring that only the intended cell is active during measurement. This local control prevents cross-interference and maintains measurement precision while benefiting from the simplified common test line structure.
Data Source
AI summary
A device may include a plurality of cells. Each cell may include a field-effect transistor and a switch configured to selectively connect a second contact of the respective field-effect transistor with a common test line of the device. A controller of the device is configured to control the switch to be in a closed position. At least one pin is provided which is configured to apply a stress voltage to a common power line connected to a first contact with the field-effect transistor and to the common test line.