Elbow Contact for FET Using Vertical Epitaxial Growth

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Solution Overview

Problem

As device scaling progresses and devices are packed more tightly, the available area for contacting the active device shrinks, leading to an increase in device contact resistance, which is detrimental as intrinsic device resistance decreases to improve performance.

Innovation Solution

A field-effect transistor (FET) design that utilizes the vertical dimension by growing a semiconductor pillar on top of the source and drain regions and forming a conductive sheath alongside the gate, increasing the contact area and reducing contact resistance by using the vertical dimension to form an elbow contact, which can increase the contact area by three times compared to conventional horizontal contacts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If device scaling progresses and devices are packed more tightly to increase density, then device density increases, but contact area shrinks leading to increased contact resistance

Engineering Contradiction:
Improvedevice densityVSAvoidcontact resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent transitions from a conventional planar contact geometry to a three-dimensional vertical contact structure. The contact extends downward from the surface along the sidewalls of the trench, utilizing the vertical dimension to increase contact area. This dimensional change allows the contact to maintain low resistance even as horizontal device pitch shrinks, directly resolving the contradiction between increased device density and maintained contact quality.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10707148B2Elbow contact for field-effect transistor and manufacture thereof
Publication Date: 2020.07.07 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10707148B2 patent drawing
  • US10707148B2 patent drawing
  • US10707148B2 patent drawing

AI summary

A field-effect transistor (FET) and method of manufacture thereof include patterning a mask above a source and drain of a FET to form holes in the mask, growing epitaxial structures from the holes in the mask, and growing a doped epitaxial shell to coat sidewalls of the epitaxial structures.