FET Engager for High-Side Gate Over-Voltage Stress Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Stress testing of integrated circuits, particularly high-side gate over-voltage stress testing, is compromised by the introduction of test probes which increase capacitance and affect the performance of the circuit, reducing the reliability of the test results.
Innovation Solution
A field effect transistor (FET) engager system that electrically couples a gate driver to the gate of an FET for testing, providing a probe pad for measurement without impacting the FET's operation, and includes fail-safe mechanisms to prevent accidental turn-on, allowing for gate current measurement without test instrument capacitance interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a test probe is applied directly to the gate of an FET for stress testing, then the test can be performed, but the test probe capacitance affects the FET operation and reduces test reliability
Solution Approach 1:
The patent introduces an intermediary circuit (the FET engager with source follower buffer) between the test probe and the FET gate. This buffer circuit isolates the capacitive loading effect of the test probe from the FET gate, allowing accurate stress testing without the probe capacitance affecting FET operation. The buffer acts as a mediator that transfers the control signal while blocking the harmful capacitive effect.
Solution Approach 2:
The patent segments the testing system into distinct functional blocks: the FET engager circuit that interfaces with the FET gate, the source follower buffer that isolates capacitance effects, and the stress testing instrumentation. This segmentation allows each component to perform its specific function without interfering with others, particularly isolating the test probe capacitance from the FET gate.
2Reliability
If the gate is held at a low voltage during stress testing, then the FET remains off and testing can proceed safely, but additional circuitry is needed to maintain this state
Solution Approach 1:
The source follower buffer circuit automatically maintains the FET gate at a safe low voltage level during stress testing without requiring external control. The buffer's inherent circuit topology self-regulates to keep the gate voltage below the threshold needed to turn on the FET, providing fail-safe protection while simplifying the overall control architecture.
Solution Approach 2:
The circuit incorporates beforehand protection mechanisms by designing the FET engager and buffer circuitry to inherently prevent the gate voltage from reaching levels that would turn on the FET during stress testing. This prior cushioning ensures safe operation before any potential harmful condition can occur.
3Measurement precision
If test instrument capacitance is connected to the gate for measurement, then gate current can be measured, but the capacitance impacts FET operation
Solution Approach 1:
The source follower buffer serves as an intermediary that enables gate current measurement while blocking the capacitive loading effect from reaching the FET gate. The buffer allows the test instrument to measure current through the gate node without its capacitance directly loading the gate, thus maintaining measurement capability while eliminating the harmful effect.
Data Source
AI summary
A field effect transistor (FET) engager, for example, includes electrically coupling a gate driver to a gate of a FET for testing the FET. The FET engager further includes providing a probe pad for test instrument measurement of the FET without test instrument capacitance impacting operation of the FET. The FET engager can electrically couple to the gate of the FET hold the gate of the FET at a low voltage while the source and drains are stress tested. The FET engager provides fail-safe mechanisms against accidental turn-on of the FET during operation. The FET engager can provide a second probe pad for selective test instrument turn-on of a second FET. The FET engager can allow test instrument measurement of gate current of the FET without test instrument capacitance impacting operation of the FET.