Back-to-Back FET ESD Pulse Generator Without Mercury Relays
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Solution Overview
Problem
Conventional ESD testing systems rely on mercury-wetted relays, which are hazardous, and semiconductor switches are not fast enough to produce the large pulse voltages required for ESD testing, often leading to device damage due to leakage currents.
Innovation Solution
A system utilizing back-to-back connected FETs, powered by a test voltage source, to generate bipolar test pulses with variable amplitudes and durations, avoiding mercury and minimizing leakage currents, suitable for MM, HBM, and CDM testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional mercury-wetted relays are used to generate ESD test pulses, then the required pulse amplitudes and risetimes can be achieved, but the system uses hazardous materials and requires high maintenance
Solution Approach 1:
The patent extracts and removes the hazardous mercury-wetted relay component from the ESD testing system, replacing it with a solid-state FET-based pulse generator. This eliminates the harmful substance while maintaining the essential function of generating ESD test pulses through a fundamentally different technological approach.
Solution Approach 2:
The patent replaces the mechanical/electromagnetic mercury-wetted relay system with a solid-state electronic system using FETs (Field Effect Transistors). This substitution transitions from a mechanical contact-based system to a semiconductor-based system, eliminating hazards while achieving the required pulse characteristics through electronic switching.
2Object-affected harmful factors
If semiconductor switches are used to generate ESD test pulses, then the system becomes solid-state and safer, but the switches are not fast enough and produce leakage currents that can damage devices under test
Solution Approach 1:
The patent introduces an intermediary circuit configuration using back-to-back connected FETs with precise gate control. This intermediary structure between the power source and DUT enables the system to achieve both safety (solid-state operation) and device protection (minimal leakage) by controlling the switching behavior of the FETs to prevent harmful leakage currents while maintaining fast response times.
3Object-affected harmful factors
If standard semiconductor devices are used for ESD testing, then the system is safer than mercury relays, but the devices cannot produce the large pulse voltages required without damaging the device under test
Solution Approach 1:
The patent employs dynamic control of FET gate voltages to achieve high pulse voltage output. By dynamically adjusting the gate control signals and utilizing the rapid switching characteristics of FETs, the system can generate large voltage pulses (exceeding 200V) without the leakage current problems of conventional semiconductor switches, thereby achieving both safety and sufficient voltage capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system produces high-voltage ESD test pulses with low aberrations, complying with industry standards, and protects devices under test by preventing leakage currents, enabling reliable ESD compliance testing.
Implementation Method 1
An ESD test capacitor is situated to be charged by the test voltage source and discharged through a device under test (DUT) and the first FET and a second FET to produce a test pulse in the DUT
Implementation Method 2
first and second opto-isolators are coupled to respective gates of the first FET and the second FET and to receive the control pulse from a pulse generator
Data Source
AI summary
Electrostatic discharge (ESD) test systems include a FET-based pulse generator using pairs of back-to-back FETs coupled to produce an ESD pulse based on discharging a capacitor that is coupled in series with a device under test (DUT). A number of FETs can be selected based on an intended ESD test voltage magnitude.