N-Channel FET Gate Driver Topology for Lower Power Dissipation
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Solution Overview
Problem
Existing driver transistors for self-conducting n-channel output stage field effect transistors in push-pull circuits experience high power dissipation due to voltage resonance, leading to inefficient energy use when driving high-side output stage transistors.
Innovation Solution
The proposed device includes a driver transistor configuration where the resistor is connected between the first and second nodes, allowing the supply voltage to be applied to the control signal output, and utilizing multiple negative voltage sources to control the voltage drop across the resistor, thereby reducing power dissipation by ensuring the voltage drop is lower than the positive voltage source.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the driver transistor is used to drive a high-side output stage transistor with sufficient negative voltage at the gate electrode to reliably inhibit it, then the output stage transistor can be reliably controlled, but the voltage across the resistor becomes high leading to high power loss in the driver
Solution Approach 1:
The patent changes the connection configuration of the resistor from being connected to the positive voltage source (prior art) to being connected to the first node (source electrode of driver transistor). This parameter change in the circuit topology allows the voltage drop across the resistor to be determined by the control signal output voltage rather than the full positive supply voltage, thereby reducing power dissipation while maintaining reliable transistor inhibition through sufficient negative gate voltage.
2Reliability
If the resistor is connected to the positive voltage source as in prior art, then the driver transistor can be inhibited with negative voltage, but the high voltage across the resistor causes high power dissipation
Solution Approach 1:
The patent introduces the first node (source electrode of the driver transistor) as an intermediary connection point for the resistor. Instead of directly connecting the resistor to the positive voltage source, the resistor is connected through this intermediate node. This intermediary connection allows the system to maintain the necessary voltage conditions for reliable transistor inhibition while reducing the voltage drop across the resistor to only what is necessary for control, thereby minimizing power dissipation.
Data Source
AI summary
A device (100) for driving a self-conducting n-channel output stage field effect transistor (V1) comprising a control signal input (110), a control signal output (120) for connection to a gate electrode (V1G) of the output stage field effect transistor (V1), a first node (N1) connected to the control signal output (120), a second node (N2), and a first transistor (V4). A source electrode (V4S) of the first transistor (V4) is connected to the first node (N1), a gate electrode (V4G) of the first transistor (V4) is connected to the second node (N2) and a drain electrode (V4D) of the first transistor (V4) is either connected to the source electrode of the output field effect transistor (V1) or connected to a supply voltage (+Vdd). A resistor (R1) is connected with one end to the second node (N2). The device (100) is characterized in that the resistor (R1) is connected at the other end to the first node (N1).The first transistor (V4) can be used to cause the supply voltage (Vdd) to be applied to the control signal output when a low-level signal is applied to the control signal input (110).