Fin-shaped FET Gate Stack Segmentation for Leakage Control
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Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in forming field effect transistors (FETs) with optimal gate stack configurations that effectively modulate carrier density and reduce leakage currents, limiting the performance of transistors in terms of on-state drain current and off-state leakage current.
Innovation Solution
The method involves forming a fin-shaped structure with a gate stack on multiple sidewalls of the channel region, allowing for improved gating performance by controlling the channel length and doping levels, which enhances carrier modulation and reduces series resistance and leakage paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used to form FETs, then manufacturing process simplicity is maintained, but gate stack configuration cannot effectively modulate carrier density and reduce leakage currents
Solution Approach 1:
The gate stack is segmented into multiple distinct layers including a first gate electrode, a second gate electrode, and an intermediate layer between them. This segmentation allows each layer to be independently configured with different materials, thicknesses, and doping levels, enabling effective carrier density modulation and leakage current reduction while maintaining a systematic fabrication approach
Solution Approach 2:
Different regions of the gate stack are assigned different local properties: the first gate electrode may use one material composition while the second gate electrode uses another, and the intermediate layer has specific dielectric properties. This local quality variation allows optimization of carrier modulation in different vertical regions and targeted suppression of leakage paths without requiring complete redesign of the entire structure
2Productivity
If channel length is scaled down to improve transistor performance, then on-state drain current increases, but manufacturing precision requirements exceed photolithography capabilities
Solution Approach 1:
Instead of relying solely on horizontal channel length scaling, the invention introduces vertical dimensionality through multi-layer gate stacks with different electrode configurations. The effective channel control is achieved through the vertical arrangement of gate electrodes at different heights, allowing short channel effects to be managed while maintaining manufacturable lateral dimensions within photolithography capabilities
3Reliability
If source/drain regions are fully depleted to reduce leakage paths, then off-state leakage current decreases, but series resistance increases
Solution Approach 1:
The source and drain regions are doped with different local properties: higher doping concentrations in regions requiring low resistance contacts, and lower doping concentrations in regions where depletion is needed for leakage suppression. This spatial variation in doping quality allows simultaneous optimization of both off-state leakage and on-state resistance characteristics
Solution Approach 2:
The source and drain regions are configured asymmetrically with respect to doping levels and geometric dimensions. One side may have heavier doping to minimize contact resistance while the other side has lighter doping to enhance depletion and reduce leakage, breaking the symmetry to simultaneously address conflicting electrical requirements
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. A first source/drain layer is formed over a substrate. A channel layer is formed over the first source/drain layer. A second source/drain layer is formed over the channel layer. The first source/drain layer, the channel layer, and the second source/drain layer are patterned to form a fin-shaped structure. A gate stack is formed on a sidewall of the fin-shaped structure. The fin-shaped structure is patterned to expose a top surface of the first source/drain layer.