FET Termination Structure With Segmented Trench Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Field effect transistors (FETs) used in power management applications face challenges in achieving low on-resistance, high breakdown voltage, and ruggedness due to vulnerabilities in the termination area, particularly the innermost trenched isolation cells, which can lead to breakdown voltage deviation and reduced lifespan under high voltage conditions.
Innovation Solution
The design incorporates a semiconductor layer with an active area and a termination area featuring a plurality of active transistor cells and termination cells, where the innermost termination cell is electrically coupled to the gate regions, and the rest are electrically floating, with termination trenches lined by insulation and filled with a conduction layer, arranged in parallel to enhance breakdown voltage and ruggedness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the innermost trenched isolation cell is used to isolate the active area from the termination area, then the FET structure is simplified and manufacturing is easier, but the breakdown voltage decreases and voltage withstand properties deteriorate under high voltage conditions
Solution Approach 1:
The termination area is divided into multiple termination cells (first termination cell, second termination cell, third termination cell) arranged in sequence from the active area outward. This segmentation allows each termination cell to handle a portion of the voltage stress, preventing any single cell from experiencing excessive electric field intensity that would cause breakdown.
Solution Approach 2:
The patent transitions from a planar gate structure to a trench gate structure, adding a vertical dimension to the gate. The trench gate extends deeper into the semiconductor substrate, creating a three-dimensional configuration that improves voltage withstand properties by distributing the electric field more effectively in the vertical direction while maintaining isolation functionality.
2Reliability
If the number of FET cells in the core active area is increased to reduce on resistance, then current handling ability improves, but the complexity of the termination area increases and voltage withstand properties may deteriorate
Solution Approach 1:
Different regions of the semiconductor device are assigned different structures and functions: the active area contains high-density FET cells for current handling, while the termination area contains the segmented termination cells with trench gates for voltage withstand. This local differentiation allows each region to be optimized for its specific function without compromising the other.
Solution Approach 2:
The trench gate structure provides dynamic electric field distribution that adapts to voltage conditions. Under high voltage stress, the vertical trench configuration naturally distributes the electric field along the trench walls, providing dynamic protection that maintains voltage withstand properties regardless of the number of active FET cells.
3Ease of manufacture
If the trenched isolation cell is positioned close to the active area to improve isolation, then manufacturing is simplified, but electric field intensity increases and leads to breakdown voltage walk-out
Solution Approach 1:
The isolation function is segmented across multiple termination cells positioned at different distances from the active area. The first termination cell is closest to the active area, followed by the second, then the third termination cell. This segmentation distributes the electric field intensity across multiple interfaces, preventing concentration of stress at any single location.
Solution Approach 2:
The trench gate structure acts as an intermediary between the active area and the termination area. The trench gate extends into the substrate and provides a gradual transition zone that mediates the electric field distribution, reducing the intensity at the isolation interface while maintaining effective electrical isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces electric field intensity near the termination cells, improving breakdown voltage and extending the lifespan of FETs by shielding them from high voltage stress and preventing punch-through of the oxide layer.
Implementation Method 1
a termination insulation layer lining the termination trench sidewalls and bottom
Implementation Method 2
a termination conduction layer filling the termination trench
Implementation Method 3
This configuration effectively reduces electric field intensity near the termination cells
Data Source
AI summary
A field effect transistor (“FET”), a termination structure and associated method for manufacturing. The FET has a plurality of active transistor cells and a termination structure. The termination structure for the FET includes a plurality of termination cells arranged substantially in parallel from an inner side toward an outer side of a termination area of the FET. Each of the termination cells comprises a termination trench lined with a termination insulation layer and filled with a termination conduction layer. The innermost termination cell is electrically coupled to gate regions of the active transistor cells while the rest of the termination cells are electrically floating.