Self-Aligned Gate and Source/Drain Contacts in FET Devices
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Solution Overview
Problem
Current field effect transistor (FET) devices face challenges in reducing footprint size and preventing electrical shorts due to finite etch selectivity among dielectric materials used for liners and caps, leading to potential reliability issues and increased complexity in fabrication.
Innovation Solution
The method involves forming gate and source/drain structures with different liner and cap materials, such as metal oxides and low-k spacer materials, to achieve greater etch selectivity and reduce spacer erosion, allowing for the placement of gate contacts over active transistor devices without additional chip area, thereby increasing transistor density and reducing electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate contacts are placed over active transistor devices to increase density, then transistor density is improved, but the risk of electrical shorts increases due to finite etch selectivity
Solution Approach 1:
The patent divides the contact structure into multiple segments: gate contact, source/drain contact, and intermediate dielectric material between them. This segmentation allows each component to be optimized independently, with the dielectric material acting as an insulating barrier that prevents electrical shorts while enabling both contact types to coexist in a compact arrangement over the active device region.
Solution Approach 2:
The patent introduces an intermediate dielectric material as a mediator between the gate contact and source/drain contact. This intermediary layer provides electrical isolation, preventing shorts while allowing both contacts to be positioned close together or overlapping, thereby achieving high density without compromising reliability.
2Manufacturing precision
If different liner and cap materials are used to achieve greater etch selectivity, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies different materials (liner and cap layers) to specific local regions of the contact structure. The liner material is applied to the gate contact region while the cap material is applied to the source/drain contact region, creating locally optimized etch selectivity that enables precise patterning without requiring complex global process changes.
Solution Approach 2:
The patent employs composite material structures with distinct liner and cap layers having different etch selectivity characteristics. This composite approach allows the formation of complex 3D contact structures with high precision by leveraging the complementary properties of different materials, while the selective etching processes simplify the overall fabrication by enabling self-aligned formation.
3Manufacturing precision
If spacer erosion is reduced through selective etching, then manufacturing precision is improved, but the fabrication process becomes more complex
Solution Approach 1:
The patent changes the etch selectivity parameters by introducing liner and cap materials with distinct etch resistance properties. This parameter modification allows the spacer material to be protected during etching processes, reducing erosion and maintaining precise dimensional control without requiring additional spacer protection steps.
Solution Approach 2:
The patent applies liner and cap materials to the contact structures before the etching process that defines the source/drain regions. This preliminary action of depositing protective layers enables the subsequent etch to proceed with high precision, as the liner and cap materials are already in place to protect critical surfaces from erosion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces spacer erosion, avoids electrical shorts, and simplifies the fabrication process by using selective etching to maintain dielectric material between conductive features, enhancing the reliability and density of transistor devices.
Implementation Method 1
forming a gate liner on the gate electrodes and gate spacers... forming a source/drain liner on the source/drain contacts and gate spacers, wherein the source/drain liner is selectively etchable relative to the gate liner
Data Source
AI summary
A method of forming a transistor device is provided. The method includes forming a plurality of gate structures including a gate spacer and a gate electrode on a substrate, wherein the plurality of gate structures are separated from each other by a source/drain contact. The method further includes reducing the height of the gate electrodes to form gate troughs, and forming a gate liner on the gate electrodes and gate spacers. The method further includes forming a gate cap on the gate liner, and reducing the height of the source/drain contacts between the gate structures to form a source/drain trough. The method further includes forming a source/drain liner on the source/drain contacts and gate spacers, wherein the source/drain liner is selectively etchable relative to the gate liner, and forming a source/drain cap on the source/drain liner.