Compact FET with Self-Aligned Counter-Electrode
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing field effect transistors face challenges in compactness and fabrication complexity due to the inability to electrically distinguish gate and counter-electrodes, requiring additional control electrodes and insulating patterns, which complicates dense circuit integration and increases the risk of short-circuiting and stray capacitances.
Innovation Solution
A method for fabricating field effect transistors with self-aligned counter-electrode contacts within the gate electrode, allowing for compact design and simplified fabrication by etching the gate material and forming counter-electrode contacts directly in the gate electrode pattern, ensuring electrical connection without needing additional control electrodes or complex insulating patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a ground plane is integrated in the support substrate to control parasite effects, then control of short-channel effect is improved, but device complexity and fabrication constraints increase due to additional control electrodes
Solution Approach 1:
The patent merges the counter-electrode function with the gate electrode by forming both electrodes from the same continuous conductive material layer. This single-layer approach integrates the counter-electrode (for parasite effect control) and gate electrode (for transistor control) into one unified structure, eliminating the need for separate control electrodes and insulating patterns while maintaining both functions
2Reliability
If additional control electrodes and insulating patterns are used to connect counter-electrode, then electrical connection is achieved, but manufacturing precision requirements increase due to safety margins in dense circuits
Solution Approach 1:
The patent extracts the counter-electrode connection from the insulating pattern context and directly integrates it into the gate electrode structure. By forming the counter-electrode as part of the gate electrode's conductive layer, the connection is established without requiring separate insulating patterns, thereby eliminating safety margin constraints and reducing manufacturing precision requirements
3Reliability
If counter-electrode contact is formed through insulating pattern, then electrical connection is made, but device area increases reducing compactness
Solution Approach 1:
The patent combines the counter-electrode contact formation with the gate electrode pattern definition in a single process step. The counter-electrode contact area is defined within the gate electrode's footprint, merging two previously separate functions into one integrated structure, thereby maximizing device compactness without compromising electrical connection
Data Source
AI summary
An etching mask, comprising the delineation pattern of the gate electrode, of a source contact, a drain contact and a counter-electrode contact, is formed on a substrate of semi-conductor on insulator type. The substrate is covered by a layer of dielectric material and a gate material. The counter-electrode contact is located in the pattern of the gate electrode. The gate material is etched to define the gate electrode, the source contact and drain contacts and the counter-electrode contact. A part of the support substrate is released through the pattern of the counter-electrode contact area. An electrically conductive material is deposited on the free part of the support substrate to form the counter-electrode contact.