Positive-Logic FET Switch Bias Ladders for High Voltage RF
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Solution Overview
Problem
Existing RF switch circuits using FET stacks face challenges such as requiring negative bias voltages, high insertion loss, and vulnerability to high voltage RF signals, which limit their performance and reliability, especially in applications with stringent power and area constraints.
Innovation Solution
A positive-logic FET switch stack configuration that eliminates the need for negative bias voltages, incorporates end-cap FETs for DC blocking, and uses series-connected resistor ladders for improved voltage handling and isolation, along with AC coupling modules for enhanced RF performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If FET stacks are used to withstand high voltage, then voltage handling capability is improved, but insertion loss increases and isolation deteriorates
Solution Approach 1:
The FET stack is segmented into multiple individual FETs connected in series, where each FET handles a portion of the total voltage. This segmentation allows each device to operate within its voltage rating while collectively withstanding high voltages, and enables independent optimization of each FET's characteristics to minimize insertion loss.
Solution Approach 2:
Different FETs within the stack are assigned different gate control voltages and biasing conditions tailored to their specific positions and functions. The gate resistor values are locally optimized for each FET to balance voltage distribution and minimize overall insertion loss, rather than using uniform parameters throughout the stack.
2Reliability
If negative bias voltages are applied to turn FETs OFF, then isolation is improved, but device complexity and power consumption increase due to charge pump requirements
Solution Approach 1:
Instead of applying negative voltages to turn FETs OFF as in conventional designs, this invention applies positive gate control voltages. The FETs are turned OFF by removing or reducing the positive gate voltage, eliminating the need for negative bias generation while achieving the required isolation through the inherent cutoff behavior of the FETs.
Solution Approach 2:
The biasing scheme uses the available positive supply voltage to control all FET gates directly, allowing the system to self-bias without external negative voltage generation. The gate resistors form simple voltage dividers that automatically establish appropriate gate voltages from the positive supply, eliminating complex bias generation circuitry.
3Ease of operation
If dedicated gate resistors are provided for each FET, then switching control is improved, but IC area consumption increases
Solution Approach 1:
Adjacent gate resistors are merged into shared resistive structures that serve multiple FET gates simultaneously. This combining approach maintains individual gate control capability while reducing the total number of discrete resistor components, thereby decreasing the overall IC area required for the switch circuit.
Solution Approach 2:
Each gate resistor is designed to serve dual purposes: providing gate bias control for its associated FET and simultaneously functioning as part of the voltage distribution network for neighboring FETs. This multi-functionality reduces the total component count and IC area while preserving switching control performance.
Data Source
AI summary
A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.