FET Source/Drain Trench Isolation for Lower RF Junction Capacitance
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Solution Overview
Problem
RF devices manufactured on bulk silicon substrates suffer from high source/drain junction capacitance, degraded linearity, harmonics, and noise, leading to increased costs due to the need for high resistivity silicon wafers to achieve desired performance.
Innovation Solution
Incorporating shallow trench isolation structures within the source/drain regions of semiconductor substrates, which reduce capacitance without degrading contact resistance and mimic the benefits of SOI substrates, such as higher resistivity and improved linearity, by using techniques like photolithographic patterning and etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If RF devices are manufactured on bulk silicon substrates, then manufacturing cost is reduced, but source/drain junction capacitance increases and linearity degrades
Solution Approach 1:
The bulk silicon substrate is segmented by introducing shallow trench isolation structures that divide the continuous substrate into isolated regions. These trenches physically separate the source/drain junctions, reducing the capacitive coupling between them while maintaining the cost advantage of bulk silicon manufacturing.
Solution Approach 2:
An intermediary insulating layer is introduced in the form of shallow trench isolation structures within the source/drain regions. This intermediary material acts as a dielectric barrier that reduces junction capacitance without requiring a complete transition to expensive SOI substrates.
2Reliability
If high resistivity silicon wafers are used, then RF linearity is improved, but manufacturing cost increases
Solution Approach 1:
Instead of requiring globally high resistivity silicon wafers, the invention applies local quality improvements by introducing shallow trench isolation structures specifically in the source/drain regions. This localized approach achieves the necessary RF linearity only where needed, avoiding the cost of expensive high resistivity substrates across the entire device.
Solution Approach 2:
The invention copies the beneficial effect of SOI substrates (vertical isolation and linearity) by implementing shallow trench isolation structures that mimic the isolation properties of SOI without requiring the expensive SOI wafer substrate itself.
3Reliability
If shallow trench isolation structures are added within source/drain regions, then capacitance is reduced, but device complexity increases
Solution Approach 1:
The invention addresses capacitance reduction by moving to another dimension - introducing vertical trench structures that extend into the substrate. This vertical dimension provides isolation without significantly increasing the planar footprint or complexity of the surface device structure.
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.