Ferroelectric Tunnel Junction With Internal Metal Gate

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Solution Overview

Problem

Conventional ferroelectric tunnel junctions (FTJs) face challenges in forming high-performance non-volatile memory devices due to poor endurance caused by dielectric layer breakdown, requiring improvements in endurance, TER ratio, programming voltage, and area efficiency.

Innovation Solution

The design incorporates an internal metal gate structure with a high-K dielectric layer and a ferroelectric film, where the top electrode and ferroelectric layer have a smaller surface area than the internal metal layer and dielectric layer, respectively, reducing the electric displacement field in the dielectric layer and allowing for lower programming voltages, thus enhancing endurance and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional FTJ structure is used, then the device can achieve basic memory functionality, but the dielectric layer breaks down leading to poor endurance

Engineering Contradiction:
ImproveenduranceVSAvoiddielectric layer breakdown
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent segments the electric field distribution by introducing an internal metal layer that divides the dielectric layer into two regions with different areas. This segmentation allows the electric displacement field to be concentrated in a smaller area under the internal metal layer, preventing widespread dielectric breakdown and improving endurance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by creating a non-uniform area configuration where the internal metal layer has a larger area than the top electrode. This local variation in geometry creates a localized electric field distribution that protects the dielectric layer from breakdown while maintaining the desired memory functionality.

Inventive Principle:
Principle #3Local quality

2Device complexity

If the top electrode and ferroelectric layer have the same area as the internal metal layer, then the structure is simple, but the electric displacement field causes dielectric breakdown

Engineering Contradiction:
Improvestructure simplicityVSAvoiddielectric layer integrity
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent introduces asymmetry by making the internal metal layer area different from the top electrode area. Specifically, the internal metal layer has a larger area, creating an asymmetric geometry that redistributes the electric displacement field and prevents dielectric breakdown without significantly complicating the overall device structure.

Inventive Principle:
Principle #4Asymmetry

3Ease of operation

If high programming voltages are used, then the FTJ can be programmed, but power consumption increases and endurance decreases

Engineering Contradiction:
Improveprogramming capabilityVSAvoidpower consumption
Core Design Contradiction:
Ease of operationVSUse of energy by moving object

Solution Approach 1:

The patent changes the geometric parameters of the device, specifically the area relationship between the internal metal layer and top electrode. This parameter change modifies the electric field distribution and reduces the programming voltage requirement from conventional high voltages to lower voltages, thereby reducing power consumption and improving endurance.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration improves the endurance of FTJs by preventing dielectric layer breakdown, achieving a higher TER ratio, and enabling lower programming voltages, which enhances the performance and reliability of non-volatile memory devices.

Implementation Method 1

a ferroelectric layer over the internal metal layer

Methodology Applied
Scientific EffectFerroelectric polarization:

Implementation Method 2

a dielectric layer between the internal metal layer and the bottom electrode

Methodology Applied
Scientific EffectHigh-K dielectric effect: Dielectric

Implementation Method 3

The electrical resistance of the FTJ, also referred to as the tunneling electroresistance (TER) of the FTJ, is determined by the orientation of the electric polarization of the ferroelectric layer

Methodology Applied
Scientific EffectTunneling electroresistance: Electrical Resistance

Data Source

PatentUS11152456B2Ferroelectric tunnel junction with internal gate
Publication Date: 2021.10.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11152456B2 patent drawing
  • US11152456B2 patent drawing
  • US11152456B2 patent drawing

AI summary

A device includes a bottom electrode that includes a first electrically conducive material; a dielectric layer over the bottom electrode; an internal metal layer over the dielectric layer; a ferroelectric layer over the internal metal layer; and a top electrode over the ferroelectric layer, the top electrode including a second electrically conductive material, an area of the top electrode being smaller than an area of the internal metal layer.