FFS LCD Array Substrate Six-Mask Process Common Line
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Solution Overview
Problem
The existing fringe field switching (FFS) mode liquid crystal display (LCD) devices require a complex seven-mask process for substrate fabrication, leading to increased production costs and potential electrical short issues, which negatively impact aperture ratio and transmissivity.
Innovation Solution
A simplified six-mask process for fabricating the array substrate, where a single common line is formed at the center of the display region, reducing the number of mask processes and avoiding electrical shorts, while maintaining improved aperture ratio by positioning the common line between gate lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a seven-mask process is used for fabricating the array substrate, then the fabrication can be completed with conventional processes, but the production cost increases and electrical shorts may occur
Solution Approach 1:
The patent merges the common line formation with the gate line formation process by using a single mask pattern that defines both structures simultaneously. This consolidation reduces the total mask processes from seven to six, lowering production costs while maintaining electrical isolation through proper design of the merged structure where the common line is positioned between gate lines.
2Reliability
If multiple common lines are formed in the display region, then the electrical connection is improved, but the aperture ratio decreases
Solution Approach 1:
The patent segments the common electrode connection into multiple isolated common lines positioned between gate lines rather than using fewer larger common lines. This segmentation allows electrical connection to be maintained through distributed contact points while minimizing the total area occupied by common lines, thereby preserving aperture ratio.
3Reliability
If the common line is positioned closer to the pixel electrode, then the electrical connection is improved, but the risk of electrical short increases
Solution Approach 1:
The patent introduces the common line as an intermediary structure positioned between gate lines that serves as a mediator for electrical connection. This intermediary positioning allows the common electrode to connect to the common line through contact holes while maintaining safe distances from pixel electrodes, reducing electrical short risk while preserving connection reliability.
Data Source
AI summary
An array substrate for a liquid crystal display (LCD) device includes a common line and gate lines. The array substrate includes a first, second, and third passivation layer and thin film transistors (TFTs). The second passivation layer includes first and second holes respectively corresponding to a drain electrode and the common line. A common electrode on the second passivation layer includes a first opening corresponding to the TFTs and a second opening in the second hole. A drain contact hole through the third and first passivation layers exposes the drain electrode. A first common contact hole through the third passivation layer exposes the common electrode in the second hole. A second common contact hole through the third and first passivation layers exposes the common line, and a pixel electrode includes a third opening and a connection pattern connecting the common electrode to the common line on the third passivation layer.