Shared Hardware Accelerator for FFT and FIR Processing
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Solution Overview
Problem
Current technologies face inefficiencies in calculating Fast Fourier Transform (FFT) and Finite Impulse Response (FIR) values, which are crucial for signal processing in various engineering applications.
Innovation Solution
A hardware accelerator module is designed to efficiently compute both FFT and FIR values, featuring a primary logic unit and a secondary logic unit that share hardware resources, utilizing multiplexers, multipliers, adders, and subtractors to evaluate algebraic expressions based on mode selection, and supports multiple numerical representation systems, including floating point and fixed point numbers, with optional pipelining registers for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate hardware accelerators are used for FFT and FIR calculations, then each algorithm can be optimized independently, but the overall device complexity and resource consumption increase
Solution Approach 1:
The patent implements a universal hardware accelerator that can perform both FFT and FIR calculations using the same core computational resources. The architecture includes shared multipliers, adders, and control logic that can be configured through multiplexers to execute different algorithms depending on the operational mode selected by control signals. This multi-functional design eliminates the need for separate dedicated hardware blocks for each algorithm type.
Solution Approach 2:
The patent merges the computational resources required for FFT and FIR processing into a single integrated hardware accelerator. By combining the multiplier units, adder units, and control mechanisms into one shared structure, the system reduces hardware complexity while maintaining the ability to efficiently execute both algorithms. The shared registers and pipelining structures further consolidate resources that would otherwise be duplicated.
2Device complexity
If a single hardware accelerator supports both FFT and FIR modes, then hardware resources are saved, but the complexity of controlling mode switching and resource allocation increases
Solution Approach 1:
The patent employs dynamic control mechanisms including multiplexers and control logic that can switch between FFT and FIR operational modes based on incoming control signals. The architecture dynamically reconfigures the computational paths by selecting different data inputs and operation sequences according to the current mode, allowing flexible adaptation without requiring physical hardware changes. This dynamic switching capability simplifies mode selection control while maintaining resource efficiency.
3Productivity
If pipelining registers are added to the hardware accelerator, then processing speed and throughput improve, but the device complexity and latency management become more difficult
Solution Approach 1:
The patent implements pipelining registers that enable continuous processing by maintaining intermediate results between computational stages. The pipeline structure allows multiple operations to proceed simultaneously at different stages, ensuring that useful computational action continues without interruption. Registers store intermediate values that are needed by subsequent operations, enabling overlapping of FFT and FIR processing cycles and significantly improving throughput while managing latency through structured data flow control.
Data Source
AI summary
A hardware accelerator operable in an FFT mode and an FIR mode. The hardware accelerator takes input data and coefficient data and performs the calculations for the selected mode. In the FFT mode, a rate-two FFT is calculated, producing four real outputs corresponding to two complex numbers. In the FIR mode, one real output is generated. The hardware accelerator may switch from FFT mode to FIR mode using three multiplexers. All FIR components may be utilized in FFT mode. Registers may be added to provide pipelining support. The hardware accelerator may support multiple numerical-representation systems.